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College of Engineering(공과대학)School of Electrical Engineering(전기및전자공학부)EE-Conference Papers(학술회의논문)

Simulation Acceleration of Transaction-Level Models for SoC with RTL sub-blocks

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dc.contributor.authorKyung, Chong-Min-
dc.contributor.authorLee, Jae-Gon-
dc.contributor.authorYang, Wooseung-
dc.contributor.authorKwon, Young-Su-
dc.contributor.authorKim, Young-Il-
dc.date.accessioned2013-03-18T14:29:57Z-
dc.date.available2013-03-18T14:29:57Z-
dc.date.created2012-02-06-
dc.date.issued2005-
dc.identifier.citationASP-DAC'2005, v., no., pp. --
dc.identifier.urihttp://hdl.handle.net/10203/149297-
dc.languageENG-
dc.titleSimulation Acceleration of Transaction-Level Models for SoC with RTL sub-blocks-
dc.typeConference-
dc.type.rimsCONF-
dc.citation.publicationnameASP-DAC'2005-
dc.identifier.conferencecountryChina-
dc.identifier.conferencecountryChina-
dc.contributor.localauthorKyung, Chong-Min-
dc.contributor.nonIdAuthorLee, Jae-Gon-
dc.contributor.nonIdAuthorYang, Wooseung-
dc.contributor.nonIdAuthorKwon, Young-Su-
dc.contributor.nonIdAuthorKim, Young-Il-
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EE-Conference Papers(학술회의논문)
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