NEW HARDWARE-BASED CLOCK SYNCHRONISATION FOR THE BYZANTINE FAULT
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Baek, Yunju | - |
| dc.contributor.author | Lee, Heung-Kyu | - |
| dc.contributor.author | Yoon, Hyunsoo | - |
| dc.date.accessioned | 2009-12-11T03:11:22Z | - |
| dc.date.available | 2009-12-11T03:11:22Z | - |
| dc.date.issued | 1992-10-08 | - |
| dc.identifier.citation | Electronics Letters- IEE, Vol.28, No.21, pp.2018-2019 | en |
| dc.identifier.issn | 0013-5194 | - |
| dc.identifier.uri | http://hdl.handle.net/10203/14654 | - |
| dc.description.abstract | A new approach for fault-tolerant clock synchronisation which uses digital clocks instead of the conventional PLLs(phase-locked loops) is presented. In this circuit the delay time of the clock systems is much reduced and the exact maximum clock skew is obtained to guarantee the tightness of the synchronisation. | en |
| dc.language.iso | en_US | en |
| dc.publisher | Institution of Engineering and Technology | en |
| dc.subject | Computer metatheory | en |
| dc.subject | Hardware fault-tolerant clock synchronisation | en |
| dc.subject | Byzantine fault | en |
| dc.subject | Interactive convergence algorithm | en |
| dc.title | NEW HARDWARE-BASED CLOCK SYNCHRONISATION FOR THE BYZANTINE FAULT | en |
| dc.type | Article | en |
| dc.identifier.doi | 10.1049/el:19921293 | - |
- Appears in Collection
- CS-Journal Papers(저널논문)
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