Design of half-rate linear phase detector using MOS current-mode logic gates for 10-Gb/s clock and data recovery circuit
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Shin, J.-K. | - |
| dc.contributor.author | Yoo, T.-W. | - |
| dc.contributor.author | Lee, Man Seop | - |
| dc.date.accessioned | 2013-03-18T06:47:08Z | - |
| dc.date.available | 2013-03-18T06:47:08Z | - |
| dc.date.created | 2012-02-06 | - |
| dc.date.issued | 2005-02-21 | - |
| dc.identifier.citation | 7th International Conference on Advanced Communication Technology, ICACT 2005, v.1, no., pp.205 - 212 | - |
| dc.identifier.uri | http://hdl.handle.net/10203/145727 | - |
| dc.language | ENG | - |
| dc.title | Design of half-rate linear phase detector using MOS current-mode logic gates for 10-Gb/s clock and data recovery circuit | - |
| dc.type | Conference | - |
| dc.identifier.scopusid | 2-s2.0-33745002214 | - |
| dc.type.rims | CONF | - |
| dc.citation.volume | 1 | - |
| dc.citation.beginningpage | 205 | - |
| dc.citation.endingpage | 212 | - |
| dc.citation.publicationname | 7th International Conference on Advanced Communication Technology, ICACT 2005 | - |
| dc.identifier.conferencecountry | Ireland | - |
| dc.identifier.conferencecountry | Ireland | - |
| dc.contributor.localauthor | Lee, Man Seop | - |
| dc.contributor.nonIdAuthor | Shin, J.-K. | - |
| dc.contributor.nonIdAuthor | Yoo, T.-W. | - |
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