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College of Engineering(공과대학)School of Electrical Engineering(전기및전자공학부)EE-Conference Papers(학술회의논문)

Dual metal gate process scheme for wide range work function modulation and reduced Fermi level pinningDual metal gate process scheme for wide range work function modulation and reduced Fermi level pinning

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dc.contributor.authorCho, Byung Jin-
dc.contributor.authorPark, CS-
dc.contributor.authorLwin, PW-
dc.contributor.authorWong, SY-
dc.contributor.authorPu, J-
dc.contributor.authorHwang, WS-
dc.date.accessioned2013-03-18T05:16:32Z-
dc.date.available2013-03-18T05:16:32Z-
dc.date.created2012-02-06-
dc.date.issued2005-07-03-
dc.identifier.citation3rd International Conference on Materials for Advanced Technologies, v., no., pp.41 - 41-
dc.identifier.urihttp://hdl.handle.net/10203/145070-
dc.languageENG-
dc.titleDual metal gate process scheme for wide range work function modulation and reduced Fermi level pinning-
dc.title.alternativeDual metal gate process scheme for wide range work function modulation and reduced Fermi level pinning-
dc.typeConference-
dc.type.rimsCONF-
dc.citation.beginningpage41-
dc.citation.endingpage41-
dc.citation.publicationname3rd International Conference on Materials for Advanced Technologies-
dc.identifier.conferencecountrySingapore-
dc.identifier.conferencecountrySingapore-
dc.contributor.localauthorCho, Byung Jin-
dc.contributor.nonIdAuthorPark, CS-
dc.contributor.nonIdAuthorLwin, PW-
dc.contributor.nonIdAuthorWong, SY-
dc.contributor.nonIdAuthorPu, J-
dc.contributor.nonIdAuthorHwang, WS-
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EE-Conference Papers(학술회의논문)
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