High-frequency Electrical Model of Chip-to-Chip Via Interconnection for 3-D Chip Stacking Package

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dc.contributor.authorKim, Joungho-
dc.contributor.authorRyu, Chunghyun-
dc.contributor.authorChung, Daehyun-
dc.contributor.authorLee, Junho-
dc.contributor.authorLee, Kwangyong-
dc.contributor.authorOh, Taesung-
dc.date.accessioned2013-03-17T07:48:02Z-
dc.date.available2013-03-17T07:48:02Z-
dc.date.created2012-02-06-
dc.date.issued2005-10-
dc.identifier.citationIEEE 14th(13) Topical Meeting on Electrical Performance of Electronic Packaging, v., no., pp.151 - 154-
dc.identifier.urihttp://hdl.handle.net/10203/141274-
dc.languageENG-
dc.publisherIEEE-
dc.titleHigh-frequency Electrical Model of Chip-to-Chip Via Interconnection for 3-D Chip Stacking Package-
dc.typeConference-
dc.type.rimsCONF-
dc.citation.beginningpage151-
dc.citation.endingpage154-
dc.citation.publicationnameIEEE 14th(13) Topical Meeting on Electrical Performance of Electronic Packaging-
dc.contributor.localauthorKim, Joungho-
dc.contributor.nonIdAuthorRyu, Chunghyun-
dc.contributor.nonIdAuthorChung, Daehyun-
dc.contributor.nonIdAuthorLee, Junho-
dc.contributor.nonIdAuthorLee, Kwangyong-
dc.contributor.nonIdAuthorOh, Taesung-
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EE-Conference Papers(학술회의논문)
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