Area-efficient memory-based architecture for FFT processing

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dc.contributor.authorMoon, S.-C.-
dc.contributor.authorPark, In-Cheol-
dc.date.accessioned2013-03-17T07:03:44Z-
dc.date.available2013-03-17T07:03:44Z-
dc.date.created2012-02-06-
dc.date.issued2003-05-25-
dc.identifier.citationProceedings of the 2003 IEEE International Symposium on Circuits and Systems, v.5, no., pp. --
dc.identifier.issn0271-4310-
dc.identifier.urihttp://hdl.handle.net/10203/140928-
dc.languageENG-
dc.titleArea-efficient memory-based architecture for FFT processing-
dc.typeConference-
dc.identifier.scopusid2-s2.0-0038758764-
dc.type.rimsCONF-
dc.citation.volume5-
dc.citation.publicationnameProceedings of the 2003 IEEE International Symposium on Circuits and Systems-
dc.identifier.conferencecountryThailand-
dc.identifier.conferencecountryThailand-
dc.contributor.localauthorPark, In-Cheol-
dc.contributor.nonIdAuthorMoon, S.-C.-
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EE-Conference Papers(학술회의논문)
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