A 372ps 64-bit adder using fast pull-up logic in 0.18-um CMOS

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dc.contributor.authorKim, J.-
dc.contributor.authorLee, K.-
dc.contributor.authorYoo, Hoi-Jun-
dc.date.accessioned2013-03-17T02:44:27Z-
dc.date.available2013-03-17T02:44:27Z-
dc.date.created2012-02-06-
dc.date.issued2006-05-21-
dc.identifier.citationISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, v., no., pp.13 - 16-
dc.identifier.urihttp://hdl.handle.net/10203/139028-
dc.languageENG-
dc.titleA 372ps 64-bit adder using fast pull-up logic in 0.18-um CMOS-
dc.typeConference-
dc.identifier.scopusid2-s2.0-34547347615-
dc.type.rimsCONF-
dc.citation.beginningpage13-
dc.citation.endingpage16-
dc.citation.publicationnameISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems-
dc.identifier.conferencecountryGreece-
dc.identifier.conferencecountryGreece-
dc.contributor.localauthorYoo, Hoi-Jun-
dc.contributor.nonIdAuthorKim, J.-
dc.contributor.nonIdAuthorLee, K.-
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