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College of Engineering(공과대학)Dept. of Materials Science and Engineering(신소재공학과)MS-Conference Papers(학술회의논문)

Via filling for System in Packaging by using IMP, PVD, CVD, ALD and Electroplating

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dc.contributor.authorLee, Won-Jong-
dc.contributor.authorCho, BH-
dc.contributor.authorMoon, JS-
dc.date.accessioned2013-03-17T02:38:37Z-
dc.date.available2013-03-17T02:38:37Z-
dc.date.created2012-02-06-
dc.date.issued2006-01-17-
dc.identifier.citationPan Pacific Microelectronics Symposium, v., no., pp. --
dc.identifier.urihttp://hdl.handle.net/10203/138969-
dc.languageENG-
dc.titleVia filling for System in Packaging by using IMP, PVD, CVD, ALD and Electroplating-
dc.typeConference-
dc.type.rimsCONF-
dc.citation.publicationnamePan Pacific Microelectronics Symposium-
dc.identifier.conferencecountryUnited States-
dc.identifier.conferencecountryUnited States-
dc.contributor.localauthorLee, Won-Jong-
dc.contributor.nonIdAuthorCho, BH-
dc.contributor.nonIdAuthorMoon, JS-
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MS-Conference Papers(학술회의논문)
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