Energy-Efficient Instruction Cache Using Page-Based Placement

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dc.contributor.authorKim, Soontae-
dc.contributor.authorVijaykrishnan, N.-
dc.contributor.authorKandemir , M.-
dc.contributor.authorIrwin, M. J.-
dc.date.accessioned2013-03-16T23:34:11Z-
dc.date.available2013-03-16T23:34:11Z-
dc.date.created2012-02-06-
dc.date.issued2001-11-01-
dc.identifier.citationInternational Conference on Compilers, Architecture, and Synthesis for Embedded Systems, v., no., pp.229 - 237-
dc.identifier.urihttp://hdl.handle.net/10203/137325-
dc.description.abstractEnergy consumption is a crucial factor in designing battery-operated embedded and mobile systems. The memory system is a major contributor to the system energy in such environments. In order to optimize energy and energy-delay in the memory system, we investigate ways of splitting the instruction cache into several smaller units, each of which is a cache by itself (called subcache). The subcache architecture employs a page-based placement strategy, a dynamic cache line remapping policy and a predictive precharging policy in order to improve the memory system energy behavior. Using applications from the SPECjvm98 and SPECint2000 benchmarks, the proposed subcache architecture is shown to be effective in improving both the energy and energy-delay metrics.-
dc.languageENG-
dc.titleEnergy-Efficient Instruction Cache Using Page-Based Placement-
dc.typeConference-
dc.type.rimsCONF-
dc.citation.beginningpage229-
dc.citation.endingpage237-
dc.citation.publicationnameInternational Conference on Compilers, Architecture, and Synthesis for Embedded Systems-
dc.contributor.localauthorKim, Soontae-
dc.contributor.nonIdAuthorVijaykrishnan, N.-
dc.contributor.nonIdAuthorKandemir , M.-
dc.contributor.nonIdAuthorIrwin, M. J.-
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CS-Conference Papers(학술회의논문)
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