A Single-chip Programmable Platform with a Multithreaded RISC and Configurable Logic Clusters(Accepted)

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This paper presents a single-chip programmable platform that integrates most of hardware blocks required in the design of embedded system chips. The platform includes a 32-bit multithreaded RISC processor (MT-RISC), configurable logic clusters (CLCs), programmable first-in-first-out (FIFO) memories, control circuitry, and on-chip memories. For rapid thread switch, a multithreaded processor equipped with a hardware thread scheduling unit is adopted, and configurable logics are grouped into clusters for IP-based design. By integrating both the multithreaded processor and the configurable logic on a single chip, high-level language-based designs can be easily accommodated by performing the complex and concurrent functions of a target chip on the multithreaded processor and implementing the external interface functions into the configurable logic clusters. A 64-mm/sup 2/ prototype chip integrating a four-threaded MT-RISC, three CLCs, programmable FIFOs, and 8-kB on-chip memories is fabricated in a 0.35-/spl mu/m CMOS technology with four metal layers, which operates at 100-MHz clock frequency and consumes 370 mW at 3.3-V power supply
Publisher
IEEE
Issue Date
2002-02-07
Language
English
Citation

International Solid-State Circuits Conference(ISSCC 2002), pp.336 - 337

URI
http://hdl.handle.net/10203/130040
Appears in Collection
NE-Conference Papers(학술회의논문)EE-Conference Papers(학술회의논문)
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