Low Jitter Digital Timing Synchronizer for CAP-based VDSL System
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Beom-Sup Kim | - |
| dc.date.accessioned | 2013-03-16T02:03:10Z | - |
| dc.date.available | 2013-03-16T02:03:10Z | - |
| dc.date.created | 2012-02-06 | - |
| dc.date.issued | 2001 | - |
| dc.identifier.citation | European Solid-State Circuits Conference, v., no., pp.146 - 147 | - |
| dc.identifier.uri | http://hdl.handle.net/10203/126296 | - |
| dc.language | ENG | - |
| dc.title | Low Jitter Digital Timing Synchronizer for CAP-based VDSL System | - |
| dc.type | Conference | - |
| dc.type.rims | CONF | - |
| dc.citation.beginningpage | 146 | - |
| dc.citation.endingpage | 147 | - |
| dc.citation.publicationname | European Solid-State Circuits Conference | - |
| dc.identifier.conferencecountry | Austria | - |
| dc.identifier.conferencecountry | Austria | - |
| dc.contributor.localauthor | Beom-Sup Kim | - |
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