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Verisim: Formal Analysis of Network SimulationsVerisim: 네트워크 시뮬레이션을 위한 정형검사기법

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dc.contributor.authorBhargavan, Karthikeyan-
dc.contributor.authorGunter, Carl A.-
dc.contributor.authorKim, Moonzoo-
dc.contributor.authorLee, Insup-
dc.contributor.authorObradovic, Davor-
dc.date.accessioned2013-03-15T23:52:47Z-
dc.date.available2013-03-15T23:52:47Z-
dc.date.created2012-02-06-
dc.date.issued2000-08-01-
dc.identifier.citationInternational Symposium on Software Testing and Analysis, v., no., pp.2 - 13-
dc.identifier.urihttp://hdl.handle.net/10203/125266-
dc.languageENG-
dc.publisherACM-
dc.titleVerisim: Formal Analysis of Network Simulations-
dc.title.alternativeVerisim: 네트워크 시뮬레이션을 위한 정형검사기법-
dc.typeConference-
dc.type.rimsCONF-
dc.citation.beginningpage2-
dc.citation.endingpage13-
dc.citation.publicationnameInternational Symposium on Software Testing and Analysis-
dc.identifier.conferencecountryUnited States-
dc.identifier.conferencecountryUnited States-
dc.contributor.localauthorKim, Moonzoo-
dc.contributor.nonIdAuthorBhargavan, Karthikeyan-
dc.contributor.nonIdAuthorGunter, Carl A.-
dc.contributor.nonIdAuthorLee, Insup-
dc.contributor.nonIdAuthorObradovic, Davor-
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CS-Conference Papers(학술회의논문)
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