DC Field | Value | Language |
---|---|---|
dc.contributor.author | Choi, Sung-Jin | ko |
dc.contributor.author | Han, Jin-Woo | ko |
dc.contributor.author | Jang, Moon-Gyu | ko |
dc.contributor.author | Choi, Yang-Kyu | ko |
dc.date.accessioned | 2009-11-10T07:24:18Z | - |
dc.date.available | 2009-11-10T07:24:18Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2009-10 | - |
dc.identifier.citation | IEEE ELECTRON DEVICE LETTERS, v.30, no.10, pp.1084 - 1086 | - |
dc.identifier.issn | 0741-3106 | - |
dc.identifier.uri | http://hdl.handle.net/10203/12362 | - |
dc.description.abstract | The aim of this letter is to analyze the spatial distribution of trapped charges in the type of dopant-segregated Schottky barrier (DSSB)-embedded FinFET SONOS devices used in NAND-type Flash memory. Due to localized programming by carrier injection with extra kinetic energy, the spatial distribution of electrons trapped in an O/N/O layer of a DSSB SONOS device after a short time of programming differs from that in an O/N/O layer of a conventional SONOS device, which results in the degradation of subthreshold slope (SS). Note that the degraded SS recovers as the program time increases. The measured and simulated data confirm that the high speed of the programming is due largely to the localized trapped charges injected from DSSB source/drain junctions. | - |
dc.description.sponsorship | the National Research Program for the 0.1-Terabit Nonvolatile Memory Development Initiative, sponsored by the Korean Ministry of Commerce, Industry and Energy | en |
dc.language | English | - |
dc.language.iso | en_US | en |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | SUBTHRESHOLD SLOPE | - |
dc.subject | MEMORY | - |
dc.title | Analysis of Trapped Charges in Dopant-Segregated Schottky Barrier-Embedded FinFET SONOS Devices | - |
dc.type | Article | - |
dc.identifier.wosid | 000270227600024 | - |
dc.identifier.scopusid | 2-s2.0-72049115242 | - |
dc.type.rims | ART | - |
dc.citation.volume | 30 | - |
dc.citation.issue | 10 | - |
dc.citation.beginningpage | 1084 | - |
dc.citation.endingpage | 1086 | - |
dc.citation.publicationname | IEEE ELECTRON DEVICE LETTERS | - |
dc.identifier.doi | 10.1109/LED.2009.2027724 | - |
dc.embargo.liftdate | 9999-12-31 | - |
dc.embargo.terms | 9999-12-31 | - |
dc.contributor.localauthor | Choi, Yang-Kyu | - |
dc.contributor.nonIdAuthor | Jang, Moon-Gyu | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Dopant-segregated Schottky barrier (DSSB) | - |
dc.subject.keywordAuthor | dopant segregation | - |
dc.subject.keywordAuthor | FinFET | - |
dc.subject.keywordAuthor | Flash memory | - |
dc.subject.keywordAuthor | localized trapping | - |
dc.subject.keywordAuthor | Schottky barrier | - |
dc.subject.keywordAuthor | SONOS | - |
dc.subject.keywordAuthor | subthreshold slope (SS) | - |
dc.subject.keywordPlus | SUBTHRESHOLD SLOPE | - |
dc.subject.keywordPlus | MEMORY | - |
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