DC Field | Value | Language |
---|---|---|
dc.contributor.author | Han, Jin-Woo | ko |
dc.contributor.author | Ryu, Seong-Wan | ko |
dc.contributor.author | Kim, Dong-Hyun | ko |
dc.contributor.author | Kim, Chung-Jin | ko |
dc.contributor.author | Kim, Sung-Ho | ko |
dc.contributor.author | Moon, Dong-Il | ko |
dc.contributor.author | Choi, Sung-Jin | ko |
dc.contributor.author | Choi, Yang-Kyu | ko |
dc.date.accessioned | 2009-11-10T07:18:27Z | - |
dc.date.available | 2009-11-10T07:18:27Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2009-07 | - |
dc.identifier.citation | IEEE ELECTRON DEVICE LETTERS, v.30, no.7, pp.742 - 744 | - |
dc.identifier.issn | 0741-3106 | - |
dc.identifier.uri | http://hdl.handle.net/10203/12361 | - |
dc.description.abstract | A capacitorless 1T-DRAM is fabricated on a fully depleted poly-Si thin-film transistor (TFT) template. A heavily doped back gate with a thin back-gate dielectric is employed to facilitate the formation of a deep potential well that retains excess holes. An asymmetric double gate (n(+) front gate and p(+) back gate) shows a wider sensing current window than a symmetric double gate (n(+) front gate and n(+) back gate). This is attributed to the inherent Hatband voltage between the p(+) back gate and the channel inducing. a deeper potential well, which a flows capacitorless 1T-DRAM operation at a low back-gate voltage. The TFT capacitorless 1T-DRAM can be applied for future stackable memory for the ultrahigh density era. | - |
dc.description.sponsorship | 0.1-Tb Nonvolatile Memory Development, sponsored by the Ministry of Knowledge Economy. | en |
dc.language | English | - |
dc.language.iso | en_US | en |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | Fully Depleted Polysilicon TFTs for Capacitorless 1T-DRAM | - |
dc.type | Article | - |
dc.identifier.wosid | 000267607900015 | - |
dc.identifier.scopusid | 2-s2.0-67650453393 | - |
dc.type.rims | ART | - |
dc.citation.volume | 30 | - |
dc.citation.issue | 7 | - |
dc.citation.beginningpage | 742 | - |
dc.citation.endingpage | 744 | - |
dc.citation.publicationname | IEEE ELECTRON DEVICE LETTERS | - |
dc.identifier.doi | 10.1109/LED.2009.2022343 | - |
dc.embargo.liftdate | 9999-12-31 | - |
dc.embargo.terms | 9999-12-31 | - |
dc.contributor.localauthor | Choi, Yang-Kyu | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Asymmetric double gate | - |
dc.subject.keywordAuthor | capacitorless 1T-DRAM | - |
dc.subject.keywordAuthor | floating-body | - |
dc.subject.keywordAuthor | fully depleted | - |
dc.subject.keywordAuthor | thin-film transistor (TFT) | - |
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