DC Field | Value | Language |
---|---|---|
dc.contributor.author | Ko, HS | ko |
dc.contributor.author | Kim, JS | ko |
dc.contributor.author | Yoon, HG | ko |
dc.contributor.author | Jang, SY | ko |
dc.contributor.author | Cho, SD | ko |
dc.contributor.author | Paik, Kyung-Wook | ko |
dc.date.accessioned | 2007-09-03T05:34:56Z | - |
dc.date.available | 2007-09-03T05:34:56Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2000-05 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON ADVANCED PACKAGING, v.23, no.2, pp.252 - 256 | - |
dc.identifier.issn | 1521-3323 | - |
dc.identifier.uri | http://hdl.handle.net/10203/1224 | - |
dc.description.abstract | A newly designed three dimensional (3-D) memory die stack package has been established, and the prototype of the 3-D package using mechanical dies has been successfully demonstrated. Fabrication processes of the 3-D package consist of 1) wafer cutting into die segments, 2) die passivation including sidewall insulation, 3) via opening on the original I/O pads, 4) I/O redistribution from center pads to sidewall, 5) bare die stacking using polymer adhesive, 6) sidewall interconnection, and 7) solder balls attachment. There are several significant improvements in this new 3-D package design compared with the current 3-D package concept. The unique feature of this newly developed package is the sidewall insulation of dies prior to the I/O redistribution of dies, which produces 1) better chip-to-wafer yields and 2) significant process simplification during subsequent fabrication steps. According to this design, 100% of die yields on a conventional wafer design can be obtained without any neighboring die losses which usually occur during the I/O redistribution processes of conventional 3-D package design. Furthermore, the new 3-D package design can simplify the following processes such as I/O redistribution, sidewall insulation, sidewall interconnection, and package formation. It is proven that the mechanical integrity of the prototype 3-D stacked package meets requirements of the JEDEC Level III and 85 degrees C/85% test. | - |
dc.description.sponsorship | This work was supported by LG Semicon. | en |
dc.language | English | - |
dc.language.iso | en_US | en |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | Development of three-dimensional memory die stack packages using polymer insulated sidewall technique | - |
dc.type | Article | - |
dc.identifier.wosid | 000087543700023 | - |
dc.identifier.scopusid | 2-s2.0-0033703289 | - |
dc.type.rims | ART | - |
dc.citation.volume | 23 | - |
dc.citation.issue | 2 | - |
dc.citation.beginningpage | 252 | - |
dc.citation.endingpage | 256 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON ADVANCED PACKAGING | - |
dc.embargo.liftdate | 9999-12-31 | - |
dc.embargo.terms | 9999-12-31 | - |
dc.contributor.localauthor | Paik, Kyung-Wook | - |
dc.contributor.nonIdAuthor | Ko, HS | - |
dc.contributor.nonIdAuthor | Kim, JS | - |
dc.contributor.nonIdAuthor | Yoon, HG | - |
dc.contributor.nonIdAuthor | Jang, SY | - |
dc.contributor.nonIdAuthor | Cho, SD | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | bare die stacking | - |
dc.subject.keywordAuthor | reliability tests | - |
dc.subject.keywordAuthor | sidewall insulation | - |
dc.subject.keywordAuthor | three-dimensional packaging | - |
dc.subject.keywordAuthor | vertical interconnection | - |
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