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College of Engineering(공과대학)Dept. of Nuclear and Quantum Engineering(원자력및양자공학과)NE-Conference Papers(학술회의논문)

Compact Test Generation Of Robustly Hazard-Free Tests For Path Delay Fault In Combinational Circuits Using 19-Valued Logic

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dc.contributor.authorKim, Dae Sik-
dc.contributor.authorSeong, Poong-Hyun-
dc.date.accessioned2013-03-15T17:37:44Z-
dc.date.available2013-03-15T17:37:44Z-
dc.date.created2012-02-06-
dc.date.issued1997-05-
dc.identifier.citationMaintenance And Reliability Conference, v., no., pp.24 - 24-
dc.identifier.urihttp://hdl.handle.net/10203/121917-
dc.languageENG-
dc.titleCompact Test Generation Of Robustly Hazard-Free Tests For Path Delay Fault In Combinational Circuits Using 19-Valued Logic-
dc.typeConference-
dc.type.rimsCONF-
dc.citation.beginningpage24-
dc.citation.endingpage24-
dc.citation.publicationnameMaintenance And Reliability Conference-
dc.identifier.conferencecountryUnited States-
dc.identifier.conferencecountryUnited States-
dc.contributor.localauthorSeong, Poong-Hyun-
dc.contributor.nonIdAuthorKim, Dae Sik-
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NE-Conference Papers(학술회의논문)
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