Improving two-level logic minimization technique for low power driven multilevel logic re-synthesis
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Choi Hoon | ko |
| dc.contributor.author | Hwang Seung Ho | ko |
| dc.date.accessioned | 2013-03-15T08:54:37Z | - |
| dc.date.available | 2013-03-15T08:54:37Z | - |
| dc.date.created | 2012-02-06 | - |
| dc.date.created | 2012-02-06 | - |
| dc.date.issued | 1997-08-03 | - |
| dc.identifier.citation | Proceedings of the 1997 40th Midwest Symposium on Circuits and Systems. Part 1 (of 2), pp.1026 - 1029 | - |
| dc.identifier.uri | http://hdl.handle.net/10203/118025 | - |
| dc.language | English | - |
| dc.publisher | Midwest Symposium on Circuits and Systems | - |
| dc.title | Improving two-level logic minimization technique for low power driven multilevel logic re-synthesis | - |
| dc.type | Conference | - |
| dc.identifier.wosid | 000073160900255 | - |
| dc.identifier.scopusid | 2-s2.0-0031344933 | - |
| dc.type.rims | CONF | - |
| dc.citation.beginningpage | 1026 | - |
| dc.citation.endingpage | 1029 | - |
| dc.citation.publicationname | Proceedings of the 1997 40th Midwest Symposium on Circuits and Systems. Part 1 (of 2) | - |
| dc.identifier.conferencecountry | US | - |
| dc.identifier.conferencelocation | Sacramento, CA, USA | - |
| dc.contributor.localauthor | Hwang Seung Ho | - |
| dc.contributor.nonIdAuthor | Choi Hoon | - |
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