Improving two-level logic minimization technique for low power driven multi-level logic re-synthesis

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Issue Date
1997-08-03
Language
ENG
Citation

Proceedings of the 1997 40th Midwest Symposium on Circuits and Systems. Part 1 (of 2), v.2, pp.1026 - 1029

URI
http://hdl.handle.net/10203/118025
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RIMS Conference Papers
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