Low power 100 MHz all digital delay-locked loop

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dc.contributor.authorKim, BS-
dc.contributor.authorKim, Lee-Sup-
dc.date.accessioned2013-03-15T04:36:18Z-
dc.date.available2013-03-15T04:36:18Z-
dc.date.created2012-02-06-
dc.date.issued1997-06-09-
dc.identifier.citationProceedings of the 1997 IEEE International Symposium on Circuits and Systems, ISCAS'97. Part 4 (of 4), v.3, no., pp.1820 - 1823-
dc.identifier.issn0271-4310-
dc.identifier.urihttp://hdl.handle.net/10203/116412-
dc.languageENG-
dc.titleLow power 100 MHz all digital delay-locked loop-
dc.typeConference-
dc.identifier.scopusid2-s2.0-0030648735-
dc.type.rimsCONF-
dc.citation.volume3-
dc.citation.beginningpage1820-
dc.citation.endingpage1823-
dc.citation.publicationnameProceedings of the 1997 IEEE International Symposium on Circuits and Systems, ISCAS'97. Part 4 (of 4)-
dc.identifier.conferencecountryHong Kong-
dc.identifier.conferencecountryHong Kong-
dc.contributor.localauthorKim, Lee-Sup-
dc.contributor.nonIdAuthorKim, BS-
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EE-Conference Papers(학술회의논문)
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