Low-jitter multi-phase digital DLL with closest edge selection scheme for DDR memory interface

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A multi-phase digital delay-locked loop (DLL) capable of a low-jitter feature for DDR memory interface is reported. The DLL repeatedly selects the output clock edge which is closest to the reference clock edge to reduce the total jitter. A test chip was fabricated in a 0.18um CMOS process to verify its functionality. The measured RMS and peak-to-peak jitter of the DLL are 6.2 and 20.4ps, respectively. The power consumption of the DLL is 12mW from a 1.8V supply voltage.
Publisher
IEEE
Issue Date
2008-09
Citation

IEE Electronics Letters, Vol. 44, No. 19

ISSN
0013-5194
DOI
10.1049/el:20081833
URI
http://hdl.handle.net/10203/11422
Appears in Collection
EE-Journal Papers(저널논문)
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