A multi-phase digital delay-locked loop (DLL) capable of a low-jitter feature for DDR memory interface is reported. The DLL repeatedly selects the output clock edge which is closest to the reference clock
edge to reduce the total jitter. A test chip was fabricated in a 0.18um CMOS process to verify its functionality. The measured RMS and peak-to-peak jitter of the DLL are 6.2 and 20.4ps, respectively. The power consumption of the DLL is 12mW from a 1.8V supply voltage.