Minimum-Complexity 0.35um Surface-Channel CMOS Process for Digital Logic and Analog Applications
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Euisik Yoon | - |
| dc.date.accessioned | 2013-03-14T21:17:21Z | - |
| dc.date.available | 2013-03-14T21:17:21Z | - |
| dc.date.created | 2012-02-06 | - |
| dc.date.issued | 1993 | - |
| dc.identifier.citation | International Conference on VLSI and CAD, v., no., pp.35 - 38 | - |
| dc.identifier.uri | http://hdl.handle.net/10203/113386 | - |
| dc.language | ENG | - |
| dc.title | Minimum-Complexity 0.35um Surface-Channel CMOS Process for Digital Logic and Analog Applications | - |
| dc.type | Conference | - |
| dc.type.rims | CONF | - |
| dc.citation.beginningpage | 35 | - |
| dc.citation.endingpage | 38 | - |
| dc.citation.publicationname | International Conference on VLSI and CAD | - |
| dc.identifier.conferencecountry | South Korea | - |
| dc.contributor.localauthor | Euisik Yoon | - |
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