An Educational and Learning kit for VHDL Modeling and ASIC Implementation

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dc.contributor.authorSeung-Ho Hwang-
dc.date.accessioned2013-03-14T19:11:28Z-
dc.date.available2013-03-14T19:11:28Z-
dc.date.created2012-02-06-
dc.date.issued1994-
dc.identifier.citationThe Electronic Design Autimation & Test Conference and Exhibition, v., no., pp. --
dc.identifier.urihttp://hdl.handle.net/10203/112232-
dc.languageENG-
dc.titleAn Educational and Learning kit for VHDL Modeling and ASIC Implementation-
dc.typeConference-
dc.type.rimsCONF-
dc.citation.publicationnameThe Electronic Design Autimation & Test Conference and Exhibition-
dc.contributor.localauthorSeung-Ho Hwang-
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