Two Layer Gate Insulator with ECR Thermal Oxide/LPCVD Oxide for Poly-Si TFT
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Chul-Hi Han | - |
| dc.date.accessioned | 2013-03-14T17:40:57Z | - |
| dc.date.available | 2013-03-14T17:40:57Z | - |
| dc.date.created | 2012-02-06 | - |
| dc.date.issued | 1993 | - |
| dc.identifier.citation | Japan Society of Applied Physics and Related Societies, v., no., pp.633 - | - |
| dc.identifier.uri | http://hdl.handle.net/10203/111422 | - |
| dc.language | ENG | - |
| dc.title | Two Layer Gate Insulator with ECR Thermal Oxide/LPCVD Oxide for Poly-Si TFT | - |
| dc.type | Conference | - |
| dc.type.rims | CONF | - |
| dc.citation.beginningpage | 633 | - |
| dc.citation.publicationname | Japan Society of Applied Physics and Related Societies | - |
| dc.identifier.conferencecountry | Japan | - |
| dc.identifier.conferencecountry | Japan | - |
| dc.contributor.localauthor | Chul-Hi Han | - |
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