A 36 fps SXGA 3-D display processor embedding a programmable 3-D graphics rendering engine

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In this paper, a 3-D display processor embedding a programmable 3-D graphics rendering engine is proposed. The proposed processor combines a 3-D graphics rendering engine and a 3-D image synthesis engine to support both true realism and interactivity for the future multimedia applications. Using high coherence between 3-D graphics data and 3-D display inputs, both pipelines are merged by sharing buffers such that a 3-D display engine directly uses the output of a 3-D graphics rendering engine. The merged architecture has synergetic coupling effects such as freely providing various rendering effects to 3-D images and easily computing disparities without complex extraction processes. In the 3-D image synthesis engine, we adopt view interpolation algorithm and propose real-time synthesis method, pixel-by-pixel process. The view interpolation algorithm reduces the number of images to be rendered, resulting in the reduction of external memory size to 64.8% compared to conventional synthesis process. The proposed pixel-by-pixel process synthesizes 3-D images at 36 fps through bandwidth reduction of 26.7% and decreases internal memory size to 64.2% compared to typical image-by-image process. The 3-D graphics rendering engine is programmable and supports the instruction sets of the latest 3-D graphics standard APIs, Pixel Shader 3.0 and OpenGL|ES 2.0. The die contains about 1.7M transistors, occupies 5 mm x 5 mm in 0.18 mu m CMOS and dissipates 379 mW at 1.85 V.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2008-05
Language
English
Article Type
Article; Proceedings Paper
Citation

IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.43, pp.1247 - 1259

ISSN
0018-9200
DOI
10.1109/JSSC.2008.920315
URI
http://hdl.handle.net/10203/11107
Appears in Collection
EE-Journal Papers(저널논문)
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