An Accurate Delay Modeling Technique for Switch - level Timing Verification
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Seung-Ho Hwang | - |
| dc.date.accessioned | 2013-03-14T16:34:00Z | - |
| dc.date.available | 2013-03-14T16:34:00Z | - |
| dc.date.created | 2012-02-06 | - |
| dc.date.issued | 1986 | - |
| dc.identifier.citation | ACM/IEEE Design Automation Conference, v., no., pp.227 - 233 | - |
| dc.identifier.uri | http://hdl.handle.net/10203/110800 | - |
| dc.language | ENG | - |
| dc.title | An Accurate Delay Modeling Technique for Switch - level Timing Verification | - |
| dc.type | Conference | - |
| dc.type.rims | CONF | - |
| dc.citation.beginningpage | 227 | - |
| dc.citation.endingpage | 233 | - |
| dc.citation.publicationname | ACM/IEEE Design Automation Conference | - |
| dc.contributor.localauthor | Seung-Ho Hwang | - |
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