Digital error correction technique for binary decision successive approximation ADCs

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dc.contributor.authorCho, S. -H.ko
dc.contributor.authorLee, Chang-Kyoko
dc.contributor.authorSung, B. -R. -S.ko
dc.contributor.authorRyu, Seung-Takko
dc.date.accessioned2009-08-24T09:00:00Z-
dc.date.available2009-08-24T09:00:00Z-
dc.date.created2012-02-06-
dc.date.created2012-02-06-
dc.date.issued2009-04-
dc.identifier.citationELECTRONICS LETTERS, v.45, no.8, pp.395 - 396-
dc.identifier.issn0013-5194-
dc.identifier.urihttp://hdl.handle.net/10203/10722-
dc.description.abstractA digital error correction technique with negligible hardware overhead is proposed for binary successive approximation ADCs. A redundant decision phase is inserted between the normal SAR operations, and the coarse decision error caused by incomplete DAC settling is corrected by a digital code addition. The relaxed DAC settling requirement for coarse decision increases the conversion speed.-
dc.description.sponsorshipThis work was supported by the Korea Science and Engineering Foundation (KOSEF) grant funded by the Korea government (MEST) (No. R11-2005-209-06002-0). The CAD tools have been supported by IDEC of KAIST.en
dc.languageEnglish-
dc.language.isoen_USen
dc.publisherINST ENGINEERING TECHNOLOGY-IET-
dc.titleDigital error correction technique for binary decision successive approximation ADCs-
dc.typeArticle-
dc.identifier.wosid000265234100008-
dc.identifier.scopusid2-s2.0-64549139755-
dc.type.rimsART-
dc.citation.volume45-
dc.citation.issue8-
dc.citation.beginningpage395-
dc.citation.endingpage396-
dc.citation.publicationnameELECTRONICS LETTERS-
dc.identifier.doi10.1049/el.2009.3738-
dc.embargo.liftdate9999-12-31-
dc.embargo.terms9999-12-31-
dc.contributor.localauthorRyu, Seung-Tak-
dc.contributor.nonIdAuthorCho, S. -H.-
dc.contributor.nonIdAuthorSung, B. -R. -S.-
dc.type.journalArticleArticle-
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