A Fast Heuristic for Optimal CMOS Functional Cell Layout Generation
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Kyung, Chong-Min | - |
| dc.contributor.author | Kwon, Y.J. | - |
| dc.date.accessioned | 2013-03-14T07:31:13Z | - |
| dc.date.available | 2013-03-14T07:31:13Z | - |
| dc.date.created | 2012-02-06 | - |
| dc.date.issued | 1988-06 | - |
| dc.identifier.citation | International Symposium on Circuits and Systems, v., no., pp. - | - |
| dc.identifier.uri | http://hdl.handle.net/10203/106556 | - |
| dc.language | ENG | - |
| dc.title | A Fast Heuristic for Optimal CMOS Functional Cell Layout Generation | - |
| dc.type | Conference | - |
| dc.type.rims | CONF | - |
| dc.citation.publicationname | International Symposium on Circuits and Systems | - |
| dc.identifier.conferencecountry | Finland | - |
| dc.identifier.conferencecountry | Finland | - |
| dc.contributor.localauthor | Kyung, Chong-Min | - |
| dc.contributor.nonIdAuthor | Kwon, Y.J. | - |
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