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College of Engineering(공과대학)School of Electrical Engineering(전기및전자공학부)EE-Conference Papers(학술회의논문)

New approach to optimal transistor sizing in CMOS digital designs

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dc.contributor.authorLee Sang Heon-
dc.contributor.authorKim Kyung Ho-
dc.contributor.authorLee Young Keun-
dc.contributor.authorPark, Song Bai-
dc.date.accessioned2013-03-14T06:42:33Z-
dc.date.available2013-03-14T06:42:33Z-
dc.date.created2012-02-06-
dc.date.issued1991-06-16-
dc.identifier.citationChina 1991 International Conference on Circuits and Systems. Part 1 (of 2), v., no., pp.415 - 418-
dc.identifier.urihttp://hdl.handle.net/10203/106225-
dc.languageENG-
dc.titleNew approach to optimal transistor sizing in CMOS digital designs-
dc.typeConference-
dc.identifier.scopusid2-s2.0-0026295073-
dc.type.rimsCONF-
dc.citation.beginningpage415-
dc.citation.endingpage418-
dc.citation.publicationnameChina 1991 International Conference on Circuits and Systems. Part 1 (of 2)-
dc.identifier.conferencecountryChina-
dc.identifier.conferencecountryChina-
dc.contributor.localauthorPark, Song Bai-
dc.contributor.nonIdAuthorLee Sang Heon-
dc.contributor.nonIdAuthorKim Kyung Ho-
dc.contributor.nonIdAuthorLee Young Keun-
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EE-Conference Papers(학술회의논문)
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