DC Field | Value | Language |
---|---|---|
dc.contributor.author | Park, Dong-Min | ko |
dc.contributor.author | Cho, Seong-Hwan | ko |
dc.date.accessioned | 2013-03-13T03:33:20Z | - |
dc.date.available | 2013-03-13T03:33:20Z | - |
dc.date.created | 2012-10-30 | - |
dc.date.created | 2012-10-30 | - |
dc.date.issued | 2012-12 | - |
dc.identifier.citation | IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.47, no.12, pp.2989 - 2998 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.uri | http://hdl.handle.net/10203/104373 | - |
dc.description.abstract | In this paper, a low-noise cascaded PLL is proposed where an integer-N digital bang-bang PLL is used to multiply a 50 MHz reference to an 800 MHz clock that is fed to a Delta Sigma fractional-N PLL to generate 2.55-to-3 GHz output. In order to minimize the jitter of the 800 MHz clock, a reference injection scheme using dual-pulse ring oscillator is employed. Quantization noise from the delta-sigma modulator is suppressed without any noise cancellation techniques owing to the high operating frequency of the fractional-N PLL. Prototype implemented in 0.13 mu m CMOS process achieves the worst-case RMS jitter of 356 fs(rms) over 100 Hz to 40 MHz integration bandwidth, while consuming 14.2 mW from a 1.2 V supply. The worst-case fractional spur measured over 7 different chips is -53.9 dBc and the reference spur is -84 dBc. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | PHASE-LOCKED LOOPS | - |
dc.subject | CHARGE PUMP | - |
dc.subject | NOISE | - |
dc.subject | OSCILLATOR | - |
dc.subject | DLL | - |
dc.title | A 14.2 mW 2.55-to-3 GHz Cascaded PLL With Reference Injection and 800 MHz Delta-Sigma Modulator in 0.13 mu m CMOS | - |
dc.type | Article | - |
dc.identifier.wosid | 000312829900012 | - |
dc.identifier.scopusid | 2-s2.0-84871762217 | - |
dc.type.rims | ART | - |
dc.citation.volume | 47 | - |
dc.citation.issue | 12 | - |
dc.citation.beginningpage | 2989 | - |
dc.citation.endingpage | 2998 | - |
dc.citation.publicationname | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.identifier.doi | 10.1109/JSSC.2012.2217856 | - |
dc.embargo.liftdate | 9999-12-31 | - |
dc.embargo.terms | 9999-12-31 | - |
dc.contributor.localauthor | Cho, Seong-Hwan | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Bang-bang | - |
dc.subject.keywordAuthor | dual-pulse ring oscillator | - |
dc.subject.keywordAuthor | fractional-N | - |
dc.subject.keywordAuthor | frequency synthesizer | - |
dc.subject.keywordAuthor | low-noise | - |
dc.subject.keywordAuthor | PLL | - |
dc.subject.keywordAuthor | reference injection | - |
dc.subject.keywordPlus | PHASE-LOCKED LOOPS | - |
dc.subject.keywordPlus | CHARGE PUMP | - |
dc.subject.keywordPlus | NOISE | - |
dc.subject.keywordPlus | OSCILLATOR | - |
dc.subject.keywordPlus | DLL | - |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.