DC Field | Value | Language |
---|---|---|
dc.contributor.author | Park, Pyoung-Won | ko |
dc.contributor.author | Park, Dong-Min | ko |
dc.contributor.author | Cho, Seong-Hwan | ko |
dc.date.accessioned | 2013-03-13T00:44:11Z | - |
dc.date.available | 2013-03-13T00:44:11Z | - |
dc.date.created | 2012-10-29 | - |
dc.date.created | 2012-10-29 | - |
dc.date.issued | 2012-10 | - |
dc.identifier.citation | IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.47, no.10, pp.2433 - 2443 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.uri | http://hdl.handle.net/10203/104033 | - |
dc.description.abstract | This paper presents a nested-PLL architecture for a low-noise wide-bandwidth fractional-N frequency synthesizer. In order to reduce the quantization noise, operating frequency of Delta Sigma S modulator (DSM) is increased by using an intermediate output of feedback divider. A PLL which serves as an anti-alias filter is added to suppress noise aliasing caused by the divider. Prototype implemented in a 0.13 mu m CMOS using ring VCOs achieves 26.3 dB of quantization noise suppression while consuming 15.2 mW and occupying 0.17 mm(2) | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | PHASE-LOCKED LOOPS | - |
dc.subject | RING-OSCILLATOR | - |
dc.subject | LOW-NOISE | - |
dc.subject | CMOS | - |
dc.title | A 2.4 GHz Fractional-N Frequency Synthesizer With High-OSR Delta Sigma Modulator and Nested PLL | - |
dc.type | Article | - |
dc.identifier.wosid | 000309741200015 | - |
dc.identifier.scopusid | 2-s2.0-84867402010 | - |
dc.type.rims | ART | - |
dc.citation.volume | 47 | - |
dc.citation.issue | 10 | - |
dc.citation.beginningpage | 2433 | - |
dc.citation.endingpage | 2443 | - |
dc.citation.publicationname | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.identifier.doi | 10.1109/JSSC.2012.2209809 | - |
dc.embargo.liftdate | 9999-12-31 | - |
dc.embargo.terms | 9999-12-31 | - |
dc.contributor.localauthor | Cho, Seong-Hwan | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Fractional-N frequency synthesizer | - |
dc.subject.keywordAuthor | high-OSR DSM | - |
dc.subject.keywordAuthor | nested-PLL | - |
dc.subject.keywordAuthor | quantization noise reduction | - |
dc.subject.keywordPlus | PHASE-LOCKED LOOPS | - |
dc.subject.keywordPlus | LOW-NOISE | - |
dc.subject.keywordPlus | CMOS | - |
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