Design of a Readout Circuit for Improving the SNR of Satellite Infrared Time Delay and Integration Arrays

Abstract

This paper presents a novel CMOS readout circuit for satellite infrared time delay and integration (TDI) arrays. An integrate-while-read method is adopted, and a dead-pixel-elimination circuit for solving a critical problem of the TDI scheme is integrated within a chip. In addition, an adaptive charge capacity control method is proposed to improve the signal-to-noise ratio (SNR) for low-temperature targets. The readout circuit was fabricated with a 0.35-mu m CMOS process for a 500 x 4 mid-wavelength infrared (MWIR) HgCdTe detector array. Using the circuit, a 90% background-limited infrared photodetection (BLIP) is satisfied over a wide input range (similar to 200-330 K), and the SNR is improved by 11 dB for the target temperature of 200 K.