DC Field | Value | Language |
---|---|---|
dc.contributor.author | Han, Jinho | ko |
dc.contributor.author | Yang, Jaehyeok | ko |
dc.contributor.author | Bae, Hyeon-Min | ko |
dc.date.accessioned | 2013-03-12T14:32:57Z | - |
dc.date.available | 2013-03-12T14:32:57Z | - |
dc.date.created | 2012-07-27 | - |
dc.date.created | 2012-07-27 | - |
dc.date.issued | 2012-06 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.59, no.6, pp.336 - 340 | - |
dc.identifier.issn | 1549-7747 | - |
dc.identifier.uri | http://hdl.handle.net/10203/102599 | - |
dc.description.abstract | This brief presents a theoretical analysis of the stochastic reference clock generator (SRCG), which creates a clocklike periodic signal from a random nonreturn-to-zero data sequence. The output of the SRCG can be utilized as a reference clock for frequency acquisition in dual-loop clock-and-data recovery circuits. A frequency-locked loop (FLL) subsequent to the SRCG guides the voltage-controlled oscillator frequency into the pull-in range of the phase-locked loop while suppressing the high-frequency phase noise of the SRCG. The phase noise and frequency offset of the SRCG-FLL pair are analyzed. The validity of the theoretical analysis is supported by results taken from a test chip. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | CDR | - |
dc.title | Analysis of a Frequency Acquisition Technique With a Stochastic Reference Clock Generator | - |
dc.type | Article | - |
dc.identifier.wosid | 000305585800004 | - |
dc.identifier.scopusid | 2-s2.0-84862516459 | - |
dc.type.rims | ART | - |
dc.citation.volume | 59 | - |
dc.citation.issue | 6 | - |
dc.citation.beginningpage | 336 | - |
dc.citation.endingpage | 340 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | - |
dc.identifier.doi | 10.1109/TCSII.2012.2195059 | - |
dc.contributor.localauthor | Bae, Hyeon-Min | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Data divider | - |
dc.subject.keywordAuthor | frequency-locked loop (FLL) | - |
dc.subject.keywordAuthor | phase noise | - |
dc.subject.keywordAuthor | referenceless clock-and-data recovery (CDR) | - |
dc.subject.keywordPlus | CDR | - |
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