DC Field | Value | Language |
---|---|---|
dc.contributor.author | Bae, YD | ko |
dc.contributor.author | Park, SI | ko |
dc.contributor.author | Park, In-Cheol | ko |
dc.date.accessioned | 2007-08-09T07:40:37Z | - |
dc.date.available | 2007-08-09T07:40:37Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2003-10 | - |
dc.identifier.citation | IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.38, pp.1703 - 1711 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.uri | http://hdl.handle.net/10203/1010 | - |
dc.description.abstract | This paper presents a single-chip programmable platform that integrates most of hardware blocks required in the design of embedded system chips. The platform includes a 32-bit multithreaded RISC processor (MT-RISC), configurable logic clusters (CLCs), programmable first-in-first-out (FIFO) memories, control circuitry, and on-chip memories. For rapid thread switch, a multithreaded processor equipped with a hardware thread scheduling unit is adopted, and configurable logics are grouped into clusters for IP-based design. By integrating both the multithreaded processor and the configurable logic on a single chip, high-level language-based designs can be easily accommodated by per-forming the complex and concurrent functions of a target chip on the multithreaded processor and implementing the external interface functions into the configurable logic clusters. A 64-mm(2) prototype chip integrating a four-threaded MT-RISC, three CLCs, programmable FIFOs, and 8-kB on-chip memories is fabricated in a 0.35-mum CMOS technology with four metal layers, which operates at 100-MHz clock frequency and consumes 370 mW at 3.3-V power supply. | - |
dc.description.sponsorship | This work was supported by the Korea Science and Engineering Foundation through the MICROS Center, by the Ministry of Science and Technology and the Ministry of Commerce, Industry, and Energy through the Project System IC 2010, and by the IC Design Education Center (IDEC). | en |
dc.language | English | - |
dc.language.iso | en_US | en |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | SYSTEM | - |
dc.title | A single-chip programmable platform based on a multithreaded processor and configurable logic clusters | - |
dc.type | Article | - |
dc.identifier.wosid | 000185568500014 | - |
dc.identifier.scopusid | 2-s2.0-0141989577 | - |
dc.type.rims | ART | - |
dc.citation.volume | 38 | - |
dc.citation.beginningpage | 1703 | - |
dc.citation.endingpage | 1711 | - |
dc.citation.publicationname | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.embargo.liftdate | 9999-12-31 | - |
dc.embargo.terms | 9999-12-31 | - |
dc.contributor.localauthor | Park, In-Cheol | - |
dc.contributor.nonIdAuthor | Bae, YD | - |
dc.contributor.nonIdAuthor | Park, SI | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | hardware platform | - |
dc.subject.keywordAuthor | multithreading | - |
dc.subject.keywordAuthor | platform-based design | - |
dc.subject.keywordAuthor | programmable logic | - |
dc.subject.keywordAuthor | system-on-chip design | - |
dc.subject.keywordPlus | SYSTEM | - |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.