Processor-based turbo interleaver for multiple third-generation wireless standards

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dc.contributor.authorShin, MCko
dc.contributor.authorPark, In-Cheolko
dc.date.accessioned2007-08-09T06:52:35Z-
dc.date.available2007-08-09T06:52:35Z-
dc.date.created2012-02-06-
dc.date.created2012-02-06-
dc.date.issued2003-05-
dc.identifier.citationIEEE COMMUNICATIONS LETTERS, v.7, pp.210 - 212-
dc.identifier.issn1089-7798-
dc.identifier.urihttp://hdl.handle.net/10203/1006-
dc.description.abstractA software, turbo interleaver running. on,. a SIMD processor is presented for a turbo decoder supporting multiple 3G 3G wireless standards. To hide the timing overhead of interleaver changing, the interleaver generation is split into two parts, preprocessing and incremental on-the-fly generation. Applying the proposed approach, we implemented a W-CDMA and cdma2000 interleaver that generates one interleaved. address per cycle and occupies 10% area of the ROM implementation.-
dc.description.sponsorshipThis work was supported in part by the Korea Science and Engineering Foundation through the MICROS Center, and by the Ministry of Science and Technology and the Ministry of Commerce, Industry and Energy through the Project System IC 2010.en
dc.languageEnglish-
dc.language.isoen_USen
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.titleProcessor-based turbo interleaver for multiple third-generation wireless standards-
dc.typeArticle-
dc.identifier.wosid000182980200004-
dc.identifier.scopusid2-s2.0-0038618704-
dc.type.rimsART-
dc.citation.volume7-
dc.citation.beginningpage210-
dc.citation.endingpage212-
dc.citation.publicationnameIEEE COMMUNICATIONS LETTERS-
dc.embargo.liftdate9999-12-31-
dc.embargo.terms9999-12-31-
dc.contributor.localauthorPark, In-Cheol-
dc.contributor.nonIdAuthorShin, MC-
dc.type.journalArticleArticle-
dc.subject.keywordAuthorcdma2000-
dc.subject.keywordAuthorSIMD processor-
dc.subject.keywordAuthorturbo interleaver-
dc.subject.keywordAuthorW-CDMA-
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