A 5.4/2.7/1.62-Gb/s Receiver for DisplayPort Version 1.2 With Multi-Rate Operation Scheme

Cited 16 time in webofscience Cited 0 time in scopus
  • Hit : 456
  • Download : 817
DC FieldValueLanguage
dc.contributor.authorLee, Won-Youngko
dc.contributor.authorHwang, Kyu-Dongko
dc.contributor.authorKim, Lee-Supko
dc.date.accessioned2013-03-11T23:31:24Z-
dc.date.available2013-03-11T23:31:24Z-
dc.date.created2012-05-25-
dc.date.created2012-05-25-
dc.date.issued2012-12-
dc.identifier.citationIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.59, no.12, pp.2858 - 2866-
dc.identifier.issn1549-8328-
dc.identifier.urihttp://hdl.handle.net/10203/100677-
dc.description.abstractA 5.4/2.7/1.62-Gb/s multi-rate receiver is designed for DisplayPort version 1.2. A dual-mode binary phase detector supports half-rate and quarter-rate phase detections to enable the multi-rate operation of the receiver without a wide-tuning VCO. In addition, a low voltage-drop active inductor with a voltage booster is implemented in the dual-mode binary phase detector to extend the bandwidth and reduce the power consumption. The voltage booster generates 1.904 V from 1.2-V supply with fast voltage generation time and small area consumption. A bandwidth controllable equalizer is proposed to optimize channel loss compensation even if the Nyquist frequency of input data changes. The BER for all input data rates is less than 10(-12) for 2(7)-1 PRBS and the measured jitter characteristics indicate that the proposed receiver exceeds the DisplayPort jitter tolerance specification. The recovered 1.35-GHz clock shows the peak-to-peak jitter of 29.9 ps and the rms jitter of 3.215 ps for 5.4-Gb/s input. The energy efficiency of the CDR circuit in the receiver is 19.3 pJ/bit at 5.4 Gb/s. The receiver occupies 0.672 mm(2) including decoupling capacitors and the CDR core area is 0.44 mm(2)-
dc.languageEnglish-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.subjectDATA RECOVERY CIRCUIT-
dc.subjectFREQUENCY ACQUISITION-
dc.subjectCMOS TECHNOLOGY-
dc.subjectRATE CDR-
dc.subjectCLOCK-
dc.subjectEQUALIZER-
dc.subjectDETECTOR-
dc.titleA 5.4/2.7/1.62-Gb/s Receiver for DisplayPort Version 1.2 With Multi-Rate Operation Scheme-
dc.typeArticle-
dc.identifier.wosid000311803300006-
dc.identifier.scopusid2-s2.0-84870539817-
dc.type.rimsART-
dc.citation.volume59-
dc.citation.issue12-
dc.citation.beginningpage2858-
dc.citation.endingpage2866-
dc.citation.publicationnameIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS-
dc.identifier.doi10.1109/TCSI.2012.2206456-
dc.contributor.localauthorKim, Lee-Sup-
dc.type.journalArticleArticle-
dc.subject.keywordAuthorClock and data recovery-
dc.subject.keywordAuthorequalizer-
dc.subject.keywordAuthormulti-rate operation-
dc.subject.keywordPlusDATA RECOVERY CIRCUIT-
dc.subject.keywordPlusFREQUENCY ACQUISITION-
dc.subject.keywordPlusCMOS TECHNOLOGY-
dc.subject.keywordPlusRATE CDR-
dc.subject.keywordPlusCLOCK-
dc.subject.keywordPlusEQUALIZER-
dc.subject.keywordPlusDETECTOR-
This item is cited by other documents in WoS
⊙ Detail Information in WoSⓡ Click to see webofscience_button
⊙ Cited 16 items in WoS Click to see citing articles in records_button

qr_code

  • mendeley

    citeulike


rss_1.0 rss_2.0 atom_1.0