DC Field | Value | Language |
---|---|---|
dc.contributor.author | Lee, Won-Young | ko |
dc.contributor.author | Hwang, Kyu-Dong | ko |
dc.contributor.author | Kim, Lee-Sup | ko |
dc.date.accessioned | 2013-03-11T23:31:24Z | - |
dc.date.available | 2013-03-11T23:31:24Z | - |
dc.date.created | 2012-05-25 | - |
dc.date.created | 2012-05-25 | - |
dc.date.issued | 2012-12 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.59, no.12, pp.2858 - 2866 | - |
dc.identifier.issn | 1549-8328 | - |
dc.identifier.uri | http://hdl.handle.net/10203/100677 | - |
dc.description.abstract | A 5.4/2.7/1.62-Gb/s multi-rate receiver is designed for DisplayPort version 1.2. A dual-mode binary phase detector supports half-rate and quarter-rate phase detections to enable the multi-rate operation of the receiver without a wide-tuning VCO. In addition, a low voltage-drop active inductor with a voltage booster is implemented in the dual-mode binary phase detector to extend the bandwidth and reduce the power consumption. The voltage booster generates 1.904 V from 1.2-V supply with fast voltage generation time and small area consumption. A bandwidth controllable equalizer is proposed to optimize channel loss compensation even if the Nyquist frequency of input data changes. The BER for all input data rates is less than 10(-12) for 2(7)-1 PRBS and the measured jitter characteristics indicate that the proposed receiver exceeds the DisplayPort jitter tolerance specification. The recovered 1.35-GHz clock shows the peak-to-peak jitter of 29.9 ps and the rms jitter of 3.215 ps for 5.4-Gb/s input. The energy efficiency of the CDR circuit in the receiver is 19.3 pJ/bit at 5.4 Gb/s. The receiver occupies 0.672 mm(2) including decoupling capacitors and the CDR core area is 0.44 mm(2) | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | DATA RECOVERY CIRCUIT | - |
dc.subject | FREQUENCY ACQUISITION | - |
dc.subject | CMOS TECHNOLOGY | - |
dc.subject | RATE CDR | - |
dc.subject | CLOCK | - |
dc.subject | EQUALIZER | - |
dc.subject | DETECTOR | - |
dc.title | A 5.4/2.7/1.62-Gb/s Receiver for DisplayPort Version 1.2 With Multi-Rate Operation Scheme | - |
dc.type | Article | - |
dc.identifier.wosid | 000311803300006 | - |
dc.identifier.scopusid | 2-s2.0-84870539817 | - |
dc.type.rims | ART | - |
dc.citation.volume | 59 | - |
dc.citation.issue | 12 | - |
dc.citation.beginningpage | 2858 | - |
dc.citation.endingpage | 2866 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS | - |
dc.identifier.doi | 10.1109/TCSI.2012.2206456 | - |
dc.contributor.localauthor | Kim, Lee-Sup | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Clock and data recovery | - |
dc.subject.keywordAuthor | equalizer | - |
dc.subject.keywordAuthor | multi-rate operation | - |
dc.subject.keywordPlus | DATA RECOVERY CIRCUIT | - |
dc.subject.keywordPlus | FREQUENCY ACQUISITION | - |
dc.subject.keywordPlus | CMOS TECHNOLOGY | - |
dc.subject.keywordPlus | RATE CDR | - |
dc.subject.keywordPlus | CLOCK | - |
dc.subject.keywordPlus | EQUALIZER | - |
dc.subject.keywordPlus | DETECTOR | - |
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