DC Field | Value | Language |
---|---|---|
dc.contributor.author | Lee, Ockgoo | ko |
dc.contributor.author | Han, Jeonghu | ko |
dc.contributor.author | An, Kyu Hwan | ko |
dc.contributor.author | Lee, Dong Ho | ko |
dc.contributor.author | Lee, Kun-Seok | ko |
dc.contributor.author | Hong, Songcheol | ko |
dc.contributor.author | Lee, Chang-Ho | ko |
dc.date.accessioned | 2013-03-11T23:18:04Z | - |
dc.date.available | 2013-03-11T23:18:04Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2010-10 | - |
dc.identifier.citation | IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.45, no.10, pp.2184 - 2197 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.uri | http://hdl.handle.net/10203/100643 | - |
dc.description.abstract | A cascode configuration in class-E CMOS power amplifiers (PAs) provides high reliability with respect to breakdown considerations. However, it causes a power loss due to the slow transition of a common-gate device from the triode region to the cut-off region. To minimize the power loss of cascode class-E CMOS PAs, we propose a charging acceleration technique, CAT. This method incorporates a capacitive element between the drain and the source of a common-gate device in a cascode configuration, accelerating the charging speed responsible for turning off a common-gate device instantly after a common-source device is turned off and thus minimizing power loss from the device. We compared the performance of the proposed cascode class-E PA to that of the conventional cascode class-E PA using a 0.18-mu m CMOS process. With a 3.3-V power supply, the proposed fully-integrated CMOS PA achieves 30.7 dBm of maximum output power and 45.6% of power-added efficiency (PAE) with a dynamic range of 40 dB at 1.6 GHz. According to measurements, the proposed cascode class-E PA shows improvement in PAE over the conventional class-E PA of between 5% and 9% in a 1.5 to 2.0 GHz range. | - |
dc.language | English | - |
dc.publisher | IEEE-Inst Electrical Electronics Engineers Inc | - |
dc.subject | DESIGN | - |
dc.subject | PAE | - |
dc.subject | ARCHITECTURE | - |
dc.subject | LOSSES | - |
dc.subject | MODEL | - |
dc.subject | BAND | - |
dc.title | A Charging Acceleration Technique for Highly Efficient Cascode Class-E CMOS Power Amplifiers | - |
dc.type | Article | - |
dc.identifier.wosid | 000283348800023 | - |
dc.identifier.scopusid | 2-s2.0-77957594035 | - |
dc.type.rims | ART | - |
dc.citation.volume | 45 | - |
dc.citation.issue | 10 | - |
dc.citation.beginningpage | 2184 | - |
dc.citation.endingpage | 2197 | - |
dc.citation.publicationname | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.contributor.localauthor | Hong, Songcheol | - |
dc.contributor.nonIdAuthor | Lee, Ockgoo | - |
dc.contributor.nonIdAuthor | Han, Jeonghu | - |
dc.contributor.nonIdAuthor | An, Kyu Hwan | - |
dc.contributor.nonIdAuthor | Lee, Dong Ho | - |
dc.contributor.nonIdAuthor | Lee, Kun-Seok | - |
dc.contributor.nonIdAuthor | Lee, Chang-Ho | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Cascode | - |
dc.subject.keywordAuthor | class-E | - |
dc.subject.keywordAuthor | CMOS | - |
dc.subject.keywordAuthor | impedance matching | - |
dc.subject.keywordAuthor | power amplifier (PA) | - |
dc.subject.keywordAuthor | power-combining | - |
dc.subject.keywordAuthor | transformer | - |
dc.subject.keywordPlus | DESIGN | - |
dc.subject.keywordPlus | PAE | - |
dc.subject.keywordPlus | ARCHITECTURE | - |
dc.subject.keywordPlus | LOSSES | - |
dc.subject.keywordPlus | MODEL | - |
dc.subject.keywordPlus | BAND | - |
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