A Charging Acceleration Technique for Highly Efficient Cascode Class-E CMOS Power Amplifiers

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dc.contributor.authorLee, Ockgooko
dc.contributor.authorHan, Jeonghuko
dc.contributor.authorAn, Kyu Hwanko
dc.contributor.authorLee, Dong Hoko
dc.contributor.authorLee, Kun-Seokko
dc.contributor.authorHong, Songcheolko
dc.contributor.authorLee, Chang-Hoko
dc.date.accessioned2013-03-11T23:18:04Z-
dc.date.available2013-03-11T23:18:04Z-
dc.date.created2012-02-06-
dc.date.created2012-02-06-
dc.date.issued2010-10-
dc.identifier.citationIEEE JOURNAL OF SOLID-STATE CIRCUITS, v.45, no.10, pp.2184 - 2197-
dc.identifier.issn0018-9200-
dc.identifier.urihttp://hdl.handle.net/10203/100643-
dc.description.abstractA cascode configuration in class-E CMOS power amplifiers (PAs) provides high reliability with respect to breakdown considerations. However, it causes a power loss due to the slow transition of a common-gate device from the triode region to the cut-off region. To minimize the power loss of cascode class-E CMOS PAs, we propose a charging acceleration technique, CAT. This method incorporates a capacitive element between the drain and the source of a common-gate device in a cascode configuration, accelerating the charging speed responsible for turning off a common-gate device instantly after a common-source device is turned off and thus minimizing power loss from the device. We compared the performance of the proposed cascode class-E PA to that of the conventional cascode class-E PA using a 0.18-mu m CMOS process. With a 3.3-V power supply, the proposed fully-integrated CMOS PA achieves 30.7 dBm of maximum output power and 45.6% of power-added efficiency (PAE) with a dynamic range of 40 dB at 1.6 GHz. According to measurements, the proposed cascode class-E PA shows improvement in PAE over the conventional class-E PA of between 5% and 9% in a 1.5 to 2.0 GHz range.-
dc.languageEnglish-
dc.publisherIEEE-Inst Electrical Electronics Engineers Inc-
dc.subjectDESIGN-
dc.subjectPAE-
dc.subjectARCHITECTURE-
dc.subjectLOSSES-
dc.subjectMODEL-
dc.subjectBAND-
dc.titleA Charging Acceleration Technique for Highly Efficient Cascode Class-E CMOS Power Amplifiers-
dc.typeArticle-
dc.identifier.wosid000283348800023-
dc.identifier.scopusid2-s2.0-77957594035-
dc.type.rimsART-
dc.citation.volume45-
dc.citation.issue10-
dc.citation.beginningpage2184-
dc.citation.endingpage2197-
dc.citation.publicationnameIEEE JOURNAL OF SOLID-STATE CIRCUITS-
dc.contributor.localauthorHong, Songcheol-
dc.contributor.nonIdAuthorLee, Ockgoo-
dc.contributor.nonIdAuthorHan, Jeonghu-
dc.contributor.nonIdAuthorAn, Kyu Hwan-
dc.contributor.nonIdAuthorLee, Dong Ho-
dc.contributor.nonIdAuthorLee, Kun-Seok-
dc.contributor.nonIdAuthorLee, Chang-Ho-
dc.type.journalArticleArticle-
dc.subject.keywordAuthorCascode-
dc.subject.keywordAuthorclass-E-
dc.subject.keywordAuthorCMOS-
dc.subject.keywordAuthorimpedance matching-
dc.subject.keywordAuthorpower amplifier (PA)-
dc.subject.keywordAuthorpower-combining-
dc.subject.keywordAuthortransformer-
dc.subject.keywordPlusDESIGN-
dc.subject.keywordPlusPAE-
dc.subject.keywordPlusARCHITECTURE-
dc.subject.keywordPlusLOSSES-
dc.subject.keywordPlusMODEL-
dc.subject.keywordPlusBAND-
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