Showing results 1 to 8 of 8
Decoupled SSD: Reducing Data Movement on NAND-Based Flash SSD Kim, Jiho; Jung, Myoungsoo; Kim, John, IEEE COMPUTER ARCHITECTURE LETTERS, v.20, no.2, pp.150 - 153, 2021-07 |
ECC-United Cache: Maximizing Efficiency of Error Detection/Correction Codes in Associative Cache Memories Farbeh, Hamed; Delshadtehrani, Leila; Kim, Hyeonggyu; Kim, Soontae, IEEE TRANSACTIONS ON COMPUTERS, v.70, no.4, pp.640 - 654, 2021-04 |
Energy-Efficient Symmetric BC-BCH Decoder Architecture for Mobile Storages Hwang, Seokha; Moon, Seungsik; Jung, Jaehwan; Kim, Daesung; Park, In-Cheol; Ha, Jeongseok; Lee, Youngjoo, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-I: REGULAR PAPERS, v.66, no.11, pp.4462 - 4475, 2019-11 |
Generator Polynomial Model-Based Eye Diagram Estimation Method for Bose-Chaudhuri-Hocquenghem (BCH) Code and Reed-Solomon (RS) Code Park, Junyong; Kim, Joungho, IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY, v.62, no.1, pp.240 - 248, 2020-02 |
Improving SSD Read Latency via Coding Park, Hyegyeong; Moon, Jaekyun, IEEE TRANSACTIONS ON COMPUTERS, v.69, no.12, pp.1809 - 1822, 2020-12 |
SALE: Smartly Allocating Low-Cost Many-Bit ECC for Mitigating Read and Write Errors in STT-RAM Caches Qureshi, Muhammad Avais; Park, Jungwoo; Kim, Soontae, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.28, no.6, pp.1357 - 1370, 2020-06 |
Symmetric Block-Wise Concatenated BCH Codes for NAND Flash Memories Kim, Daesung; Narayanan, Krishna R.; Ha, Jeongseok, IEEE TRANSACTIONS ON COMMUNICATIONS, v.66, no.10, pp.4365 - 4380, 2018-10 |
Two-Dimensional Error-Pattern-Correcting Codes Yoon, Sung Whan; Moon, Jaekyun, IEEE TRANSACTIONS ON COMMUNICATIONS, v.63, no.8, pp.2725 - 2740, 2015-08 |
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