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Showing results 1 to 4 of 4

1
A 21-Gbit/s 1.63-pJ/bit Adaptive CTLE and One-Tap DFE With Single Loop Spectrum Balancing Method

Kim, Yong-Hun; Kim, Young-Ju; Lee, Taeho; Kim, Lee-Sup, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.24, no.2, pp.789 - 793, 2016-02

2
A 28-Gb/s Receiver With Self-contained Adaptive Equalization and Sampling Point Control Using Stochastic Sigma-Tracking Eye-Opening Monitor

Won, Hyo Sup; Lee, Joon Yeong; Yoon, Taehun; Han, Kwangseok; Lee, Sangeun; Park, Jinho; Bae, Hyeon-min, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.64, no.3, pp.664 - 674, 2017-03

3
An 11.5 Gb/s 1/4th Baud-Rate CTLE and Two-Tap DFE With Boosted High Frequency Gain in 110-nm CMOS

Kim, Yonghun; Kim, Young Ju; Lee, Taeho; Kim, Lee-Sup, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.23, no.3, pp.588 - 592, 2015-03

4
Self-Iterating Soft Equalizer

Jeong, Seongwook; Moon, Jaekyun, IEEE TRANSACTIONS ON COMMUNICATIONS, v.61, no.9, pp.3697 - 3709, 2013-09

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