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Showing results 1 to 4 of 4

1
A 3-D Low Jitter and Skew Clock Distribution Network Scheme Using LTCC Package Level Interposer With a Planar Cavity Resonator

Lee, Woo-Jin; Kim, Jae-Min; Ryu, Chung-Hyun; Park, Jong-Bae; Kim, Jun-Chul; Kim, Joung-Ho, IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, v.19, pp.512 - 514, 2009-08

2
Chip package hybrid I/O clock distribution for 2Gbps DDR graphic memory = 2기가 bps급 DDR 그래픽 메모리를 위한 칩 패키지 하이브리드 I/O클럭 분배에 관한 연구link

Ryu, Chung-Hyun; 류충현; et al, 한국과학기술원, 2004

3
Modeling and measurement of interlevel electromagnetic coupling and fringing effect in a hierarchical power distribution network using segmentation method with resonant cavity model

Kim, Jae-Min; Jeong, You-Chul; Lee, Jun-Ho; Ryu, Chung-Hyun; Shim, Jong-Joo; Shin, Min-Chul; Kim, Joung-Ho, IEEE TRANSACTIONS ON ADVANCED PACKAGING, v.31, pp.544 - 557, 2008-08

4
System-in-package having reduced influence between conductor and antenna and method of designing the same

Kim, Joung-ho; Kim, Gawon; Ryu, Chung-Hyun, 2010-07-20

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