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A 0.89 μVrms Noise 93 dB High Dynamic Range Low Power 16 Channels Closed-Loop Neural Recording Chip Cho, Jae Ouk; Kim, Jang Hwan; Jang, Jun Tae; Kim, Hong Kyun; Kim, Chul, IDEC Journal of Integrated Circuits and Systems, v.9, no.2, pp.1 - 6, 2023-04 |
A 5-Gb/s 2.67-mW/Gb/s Digital Clock and Data Recovery With Hybrid Dithering Using a Time-Dithered Delta-Sigma Modulator Lee, Taeho; Kim, Yonghun; Sim, Jaehyeong; Park, Jun-Seok; Kim, Lee-Sup, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.24, no.4, pp.1450 - 1459, 2016-04 |
Hardware Reduction of MASH Delta-Sigma Modulator Based on Partially Folded Architecture Song, Jinook, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.62, no.10, pp.967 - 971, 2015-10 |
Spur-Free MASH Delta-Sigma Modulation Song, Jin-Ook; Park, In-Cheol, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.57, no.9, pp.2426 - 2437, 2010-09 |
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