Browse by Type Conference
Showing results 1381 to 1400 of 109522
| A 152mW/195mW Multimedia Processor with Fully Programmable 3D Graphics and MPEG/H.264/JPEG for Handheld Devices Yoo, Hoi-Jun; Woo, Jeong-Ho; Sohn, Ju-Ho; Kim, Hyejung; Jeong, Jongcheol; Jeong, Euljoo; Lee, Suk Joong, Design Automation Conference(DAC), 2007 |
| A 159.2mW SoC implementation of T-DMB receiver including stacked memories Lee, J.; Kim, S.; Kim, J.; Kim, D.; Kwon, Y.; Choi, M.; Park, K.; et al, IEEE 2008 Custom Integrated Circuits Conference, CICC 2008, pp.679 - 682, IEEE, 2008-09-21 |
| A 15μW 16 channel ExG processor with data transition memory-quad level vector for wearable healthcare platform Roh, Taehwan; Lee, SeulKi; Yoo, Hoi-Jun, IEEE Biomedical Circuits and Systems -BioCAS 2011, pp.325 - 328, IEEE, 2011-11-11 |
| A 16-channel wireless neural interfacing SoC with RF-powered energy-replenishing adiabatic stimulation Ha, Sohmyung; Akinin, Abraham; Park, Jiwoong; Kim, Chul; Wang, Hui; Maier, Christoph; Cauwenberghs, Gert; et al, 29th Annual Symposium on VLSI Circuits, VLSI Circuits 2015, pp.C106 - C107, Institute of Electrical and Electronics Engineers Inc., 2015-06 |
| A 161.6 TOPS/W Mixed-mode Computing-in-Memory Processor for Energy-Efficient Mixed-Precision Deep Neural Networks Jo, Wooyoung; Kim, Sangjin; Lee, Juhyoung; Um, Soyeon; Li, Zhiyong; Yoo, Hoi-Jun, 2022 IEEE International Symposium on Circuits and Systems, ISCAS 2022, pp.365 - 369, Institute of Electrical and Electronics Engineers Inc., 2022-05 |
| A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET Kim, Gain; Kull, Lukas; Luu, Danny; Braendli, Matthias; Menolfi, Christian; Francese, Pier-Andrea; Yueksel, Hazar; et al, IEEE International Solid- State Circuits Conference (ISSCC), pp.476 - +, IEEE, 2019-02 |
| A 16b quadrature direct digital frequency synthesizer using interpolative angle rotation algorithm Song Y.; Kim B., 2002 Symposium on VLSI Circuits Digest of Technical Papers, pp.146 - 147, IEEE, 2002-06-13 |
| A 17.5 fJ/bit Energy-efficient Analog SRAM for Mixed-signal Processing Yoo, Hoi Jun; Lee, Jinsu; Shin, Dongjoo; Kim, Youchang, IEEE International Symposium on Circuit and Systems, IEEE, 2016-05 |
| A 170MHz-Lock-In-Range and-253dB-FoM(jitter), 12-to-14.5GHz Subsampling PLL with a 150 mu W Frequency-Disturbance-Correcting Loop Using a Low-Power Unevenly Spaced Edge Generator Lim, Younghyun; Kim, Juyeop; Jo, Yongwoo; Bang, Jooeun; Yoo, Seyeon; Park, Hangi; Yoon, Heein; et al, IEEE International Solid-State Circuits Conference (ISSCC), pp.280 - 282, IEEE, 2020-02-19 |
| A 17mW, 20Mpixels/s 3-D Rendering Processor For Portable Multimedia Application 유회준, ISOCC 2005, pp.612 - 613, 2005-10 |
| A 18.5 nW 12-bit 1-kS/s Reset-Energy Saving SAR ADC for Bio-Signal Acquisition in 0.18-um CMOS Seo, Min-Jae; Jin, Dong-Hwan; Kim, Ye-Dam; Hwang, Sun-Il; Kim, Jong-Pal; Ryu, Seung-Tak, International Symposium on Integrated Circuits and Systems, pp.3617 - 3627, IEEE CAS Society, 2018-09-02 |
| A 185fsrms-integrated-jitter and -245dB FOM PVT-robust ring-VCO-based injection-locked clock multiplier with a continuous frequency-tracking loop using a replica-delay cell and a dual-edge phase detector Choi, Seojin; Yoo, Seyeon; Choi, Jaehyouk, 63rd IEEE International Solid-State Circuits Conference, ISSCC 2016, pp.194 - 195, Institute of Electrical and Electronics Engineers Inc., 2016-02-15 |
| A 186Mvertices/s 161mW floating-point vertex processor for mobile graphics systems Yu, C.-H.; Chung, K.; Kim, D.; Kim, Lee-Sup, 2007 IEEE Custom Integrated Circuits Conference, CICC, pp.579 - 582, 2007-09-16 |
| A 187dB FoMS 46fJ/Conv. 2nd-order Highpass ΔΣ Capacitance-to-Digital Converter Jung, Yoontae; Oh, Sein; Koo, Jimin; Park, Seunga; Suh, Ji-Hoon; Cho, Donghee; Ha, Sohmyung; et al, 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), IEEE, 2023-06-11 |
| A 188fsrms-Jitter and -243d8-FoMjitter5.2GHz-Ring-DCO-Based Fractional-N Digital PLL with a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector Hwang, Chanwoong; Park, Hangi; Seong, Taeho; Choi, Jaehyouk, 2022 IEEE International Solid-State Circuits Conference, ISSCC 2022, pp.378 - 380, Institute of Electrical and Electronics Engineers Inc., 2022-02 |
| A 195mW, 9.1Mvertices/s fully programmable 3D graphics processor for low power mobile devices Woo, J.-H.; Sohn, J.-H.; Kim, H.; Jeong, J.; Jeong, E.; Lee, S.-J.; Yoo, Hoi-Jun, 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC, pp.372 - 375, 123, 2007-11-12 |
| A 1GHz 1.3dB NF +13dBm Output P1dB SOI CMOS Low Noise Amplifier for SAW-less Receivers Kim, B.-K.; Im, D; Choi, J; Lee, Kwyro, 2012 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2012, IEEE, 2012-06 |
| A 1GHz fault tolerant processor with dynamic lockstep and self-recovering cache for ADAS SoC complying with ISO26262 in automotive electronics Han, Jinho; Kwon, Youngsu; Cho, Yong Cheol; Yoo, Hoi-Jun, IEEE Asian Solid-State Circuits Conference 2017, IEEE Asian Solid-State Circuits Conference 2017, 2017-11 |
| A 1Mb/s, -75dBm sensitive fully integrated body channel transceiver for a low energy compact wearable healthcare sensor Yan, L.; Bae, J.; Yoo, Hoi-Jun, 2010 6th IEEE Asian Solid-State Circuits Conference, A-SSCC 2010, pp.233 - 236, IEEE, 2010-11-08 |
| A 1mJ/frame Unified Media Application Processor with a 179.7pJ Mixed-Mode Feature Extraction Engine for Embedded 3D-Media Contents Processing Kim, Hyo-Eun; Park, Jun-Seok; Yoon, Jae-Sung; Kim, Seok-Hoon; Kim, Lee-Sup, 2012 IEEE Custom Integrated Circuits Conference, IEEE, 2012-09-11 |
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