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Cho, SeongHwan (조성환)
교수, School of Electrical Engineering(전기및전자공학부)
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    NO Title, Author(s) (Publication Title, Volume Issue, Page, Issue Date)
    1
    An On-Chip Thermal Monitoring System With a Temperature Sensing Area of 52 mu m(2) in 180-nm CMOS

    Jung, Dong-Kyun; Seo, Jin-O; Cho, Seonghwanresearcher, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.66, no.10, pp.1638 - 1642, 2019-10

    2
    A 2.92-mu W Capacitance-to-Digital Converter With Differential Bondwire Accelerometer, On-Chip Air Pressure, and Humidity Sensor in 0.18-mu m CMOS

    Park, Sujin; Lee, Geon-Hwi; Cho, SeongHwanresearcher, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.54, no.10, pp.2845 - 2856, 2019-10

    3
    A Second-Order Delta Sigma Time-to-Digital Converter Using Highly Digital Time-Domain Arithmetic Circuits

    Kim, Dongin; Kim, Kwangseok; Yu, Wonsik; et al, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.66, no.10, pp.1643 - 1647, 2019-10

    4
    A Hybrid PLL Using Low-Power GRO-TDC for Reduced In-Band Phase Noise

    Kim, Dongin; Cho, Seonghwanresearcher, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.66, no.2, pp.232 - 236, 2019-02

    5
    A Low-Power Photoplethysmogram-Based Heart Rate Sensor Using Heartbeat Locked Loop

    Lee, Jinseok; Jang, Do-Hun; Park, Sujin; et al, IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS, v.12, no.6, pp.1220 - 1229, 2018-12

    6
    A 3.2-GHz Supply Noise-Insensitive PLL Using a Gate-Voltage-Boosted Source-Follower Regulator and Residual Noise Cancellation

    Jo, Youngwoo; Kim, Hyo Jun; Cho, Seonghwanresearcher, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.26, no.10, pp.2170 - 2174, 2018-10

    7
    An Ultra-High Input Impedance Analog Front End Using Self-Calibrated Positive Feedback

    Lee, Jinseok; Lee, Geon-Hwi; Kim, Hyo Jun; et al, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.53, no.8, pp.2252 - 2262, 2018-08

    8
    Self-Powered Wearable Electrocardiography Using a Wearable Thermoelectric Power Generator

    Kim, Choong Sun; Yang, Hyeong Man; Lee Jinseok; et al, ACS ENERGY LETTERS , v.3, no.3, pp.501 - 507, 2018-03

    9
    A 2.4-GHz 1.5-mW Digital Multiplying Delay-Locked Loop Using Pulsewidth Comparator and Double Injection Technique

    Kim, Hyunik; Kim, Yongjo; Kim, Taeik; et al, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.52, no.11, pp.2934 - 2946, 2017-11

    10
    A Relative Permittivity-Based Air Pressure Sensor Using Standard CMOS Process

    Kang, John H.; Park, Sujin; Cho, SeongHwanresearcher, IEEE SENSORS JOURNAL, v.17, no.12, pp.3892 - 3899, 2017-06

    11
    A 2.3-mW 0.01-mm(2) 1.25-GHz Quadrature Signal Corrector With 1.1-ps Error for Mobile DRAM Interface in 65-nm CMOS

    Kim, Yongjo; Song, Keunsoo; Kim, Dongkyun; et al, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.64, no.4, pp.397 - 401, 2017-04

    12
    A 1-GS/s 9-bit Zero-Crossing-Based Pipeline ADC Using a Resistor as a Current Source

    Kim, Young-Hwa; Cho, SeongHwanresearcher, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.24, no.7, pp.2570 - 2579, 2016-07

    13
    A Hybrid-Domain Two-Step Time-to-Digital Converter Using a Switch-Based Time-to-Voltage Converter and SAR ADC

    Kim, Jungho; Kim, Young-Hwa; Kim, KwangSeok; et al, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.62, no.7, pp.631 - 635, 2015-07

    14
    A 0.22 ps(rms) Integrated Noise 15 MHz Bandwidth Fourth-Order Delta Sigma Time-to-Digital Converter Using Time-Domain Error-Feedback Filter

    Yu, Wonsik; Kim, KwangSeok; Cho, Seong-Hwanresearcher, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.50, no.5, pp.1251 - 1262, 2015-05

    15
    Integrated All Electrical Pulse Wave Velocity and Respiration Sensors Using Bio-Impedance

    Lee, Woojae; Cho, Seong-Hwanresearcher, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.50, no.3, pp.776 - 785, 2015-03

    16
    A 148fS(rms) Integrated Noise 4 MHz Bandwidth Second-Order Delta Sigma Time-to-Digital Converter With Gated Switched-Ring Oscillator

    Yu, Wonsik; Kim, KwangSeok; Cho, SeongHwanresearcher, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.61, no.8, pp.2281 - 2289, 2014-08

    17
    A 9 bit, 1.12 ps Resolution 2.5 b/ Stage Pipelined Time-to-Digital Converter in 65 nm CMOS Using Time-Register

    Kim, KwangSeok; Yu, Wonsik; Cho, SeongHwanresearcher, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.49, no.4, pp.1007 - 1016, 2014-04

    18
    A 7 bit, 3.75 ps Resolution Two-Step Time-to-Digital Converter in 65 nm CMOS Using Pulse-Train Time Amplifier

    Kim, Kwang-Seok; Kim, Young-Hwa; Yu, Won-Sik; et al, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.48, pp.1009 - 1017, 2013-04

    19
    A Time-Domain High-Order MASH Delta Sigma ADC Using Voltage-Controlled Gated-Ring Oscillator

    Yu, Won-Sik; Kim, Jae-Wook; Kim, Kwang-Seok; et al, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.60, no.4, pp.856 - 866, 2013-04

    20
    A 14.2 mW 2.55-to-3 GHz Cascaded PLL With Reference Injection and 800 MHz Delta-Sigma Modulator in 0.13 mu m CMOS

    Park, Dong-Min; Cho, Seong-Hwanresearcher, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.47, no.12, pp.2989 - 2998, 2012-12

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