Researcher Page

사진

Shin, Youngsoo (신영수) C-1621-2011

Department
School of Electrical Engineering(전기및전자공학부)
Co-author
Collaboration Network Collaboration Network
Website
http://dtlab.kaist.ac.kr/HomePage
Research Area

Keyword Cloud

Reload 더보기
1

Reliable Memristive Switching Memory Devices Enabled by Densely Packed Silver Nanocone Arrays as Electric -Field Concentrators

Shin, Youngsooresearcher; Joe, Daniel J.; Jung, Yeon Sikresearcher; You, Byoung Kuk; Yang, Kyoung-Hoonresearcher; Lee, Keon Jaeresearcher; Kim, Jong MinAMER CHEMICAL SOCACS NANO, v.10, no.10, pp.9478 - 9488, 2016-10

2

Synthesis of Dual-Mode Circuits Through Library Design, Gate Sizing, and Clock-Tree Optimization

Shin, Youngsooresearcher; Kim, Sangmin; Kang, SeokhyeongASSOC COMPUTING MACHINERYACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, v.21, no.3, 2016-07

3

Wakeup scheduling and its buffered tree synthesis for power gating circuits

Paik, Seungwhun; Shin, Youngsooresearcher; Kim, Sangmin; Kang, SeokhyeongELSEVIER SCIENCE BVINTEGRATION-THE VLSI JOURNAL, v.53, pp.157 - 170, 2016-03

4

Light Interference Map: A Prescriptive Optimization of Lithography-Friendly Layout

Shin, Youngsooresearcher; Shim, Seongbo; Choi, SuhyeongIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INCIEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, v.29, no.1, pp.44 - 49, 2016-02

5

One-Cycle Correction of Timing Errors in Pipelines With Standard Clocked Elements

Shin, Youngsooresearcher; Lin, Yu Shiang; Kim, Jae Joon; Shin, InsupIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INCIEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.24, no.2, pp.600 - 612, 2016-02

6

An Analytical Approach to Thermal Design and Optimization With a Temperature-Dependent Power Model

Shim, Seongbo; Lee, Jae Wook; Shin, YoungsooresearcherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INCIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.62, no.3, pp.816 - 824, 2015-03

7

Aggressive Voltage Scaling Through Fast Correction of Multiple Errors With Seamless Pipeline Operation

Shin, Youngsooresearcher; Kim, Jae-Joon; Shin, In-SupIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INCIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.62, no.2, pp.468 - 477, 2015-02

8

Topology-oriented pattern extraction and classification for synthesizing lithography test patterns

Shim, Seongbo; Shin, YoungsooresearcherSPIE-SOC PHOTO-OPTICAL INSTRUMENTATION ENGINEERSJOURNAL OF MICRO-NANOLITHOGRAPHY MEMS AND MOEMS, v.14, no.1, 2015-01

9

Simplifying Clock Gating Logic by Matching Factored Forms

Shin, Youngsooresearcher; Han, InhakIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INCIEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.22, no.6, pp.1338 - 1349, 2014-06

10

HAPL: Heterogeneous Array of Programmable Logic Using Selective Mask Patterning

Baek, Donkyu; Kim, Duckhwan; Paik, Seungwhun; Shin, Youngsooresearcher; Shin, In-SupIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INCIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.61, no.1, pp.146 - 159, 2014-01

11

ACCURATE GATE DELAY EXTRACTION FOR TIMING ANALYSIS OF BODY-BIASED CIRCUITS

Shin, Insup; Shin, Youngsooresearcher; Baek, DonkyuWORLD SCIENTIFIC PUBL CO PTE LTDJOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, v.22, no.8, 2013-09

12

Maximizing Frequency and Yield of Power-Constrained Designs Using Programmable Power-Gating

Kim, Nam-Sung; Shin, Young-Sooresearcher; Sinkar, Abhishek; Seomun, JunIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INCIEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.20, no.10, pp.1885 - 1890, 2012-10

13

Clock Gating Synthesis of Pulsed-Latch Circuits

Kim, Sang-Min; Shin, Young-Sooresearcher; Paik, Seung-Whun; Han, In-HakIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INCIEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.31, no.7, pp.1019 - 1030, 2012-07

14

HLS-dv: A High-Level Synthesis Framework for Dual-Vdd Architectures

Shin, In-Sup; Paik, Seung-Whun; Shin, Dong-Wan; Shin, Young-SooresearcherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INCIEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.20, no.4, pp.593 - 604, 2012-04

15

Pulsed-Latch Aware Placement for Timing-Integrity Optimization

Chang, Yao-Wen; Chuang, Yi-Lin; Shin, Youngsooresearcher; Kim, SangminIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INCIEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.30, no.12, pp.1856 - 1869, 2011-12

16

SAMPLING CORRELATION SOURCES FOR TIMING YIELD ANALYSIS OF SEQUENTIAL CIRCUITS WITH CLOCK NETWORKS

Liou, Jing-Jia; Shin, Chang-Sik; Yu, Lee-Eun; Paik, Seung-Whun; Shin, Young-SooresearcherWORLD SCIENTIFIC PUBL CO PTE LTDJOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, v.20, no.8, pp.1547 - 1569, 2011-12

17

Retiming Pulsed-Latch Circuits with Regulating Pulse Width

Lee, Seong-Gwan; Shin, Young-Sooresearcher; Paik, Seung-WhunIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INCIEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.30, no.8, pp.1114 - 1127, 2011-08

18

Design and Optimization of Power-Gated Circuits With Autonomous Data Retention

Seomun, Jun; Shin, Young-SooresearcherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INCIEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.19, no.2, pp.227 - 236, 2011-02

19

Pulsed-Latch Circuits: A New Dimension in ASIC Design

Shin, Young-Sooresearcher; Paik, Seung-WhunIEEE COMPUTER SOCIEEE DESIGN TEST OF COMPUTERS, v.28, pp.50 - 57, 2011

20

LOOKUP TABLE-BASED ADAPTIVE BODY BIASING OF MULTIPLE MACROS FOR PROCESS VARIATION COMPENSATION AND LOW LEAKAGE

Shin, Youngsooresearcher; Choi, BWORLD SCIENTIFIC PUBL CO PTE LTDJOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, v.19, no.7, pp.1449 - 1464, 2010-11

Load more items
Loading...

rss_1.0 rss_2.0 atom_1.0