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Shin, Youngsoo (신영수) C-1621-2011

Department
School of Electrical Engineering(전기및전자공학부)
Co-author
Collaboration Network Collaboration Network
Website
http://dtlab.kaist.ac.kr/HomePage
Research Area

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1

Machine Learning-Guided Etch Proximity Correction

Shim, Seongbo; Shin, YoungsooresearcherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INCIEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, v.30, no.1, pp.1 - 7, 2017-02

2

Lithography Defect Probability and Its Application to Physical Design Optimization

Shim, Seongbo; Chung, Woohyun; Shin, YoungsooresearcherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INCIEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.25, no.1, pp.271 - 285, 2017-01

3

Reliable Memristive Switching Memory Devices Enabled by Densely Packed Silver Nanocone Arrays as Electric -Field Concentrators

You, Byoung Kuk; Kim, Jong Min; Joe, Daniel J.; Yang, Kyoung-Hoonresearcher; Shin, Youngsooresearcher; Jung, Yeon Sikresearcher; Lee, Keon JaeresearcherAMER CHEMICAL SOCACS NANO, v.10, no.10, pp.9478 - 9488, 2016-10

4

Synthesis of Dual-Mode Circuits Through Library Design, Gate Sizing, and Clock-Tree Optimization

Kim, Sangmin; Kang, Seokhyeong; Shin, YoungsooresearcherASSOC COMPUTING MACHINERYACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, v.21, no.3, 2016-07

5

Wakeup scheduling and its buffered tree synthesis for power gating circuits

Kim, Sangmin; Paik, Seungwhun; Kang, Seokhyeong; Shin, YoungsooresearcherELSEVIER SCIENCE BVINTEGRATION-THE VLSI JOURNAL, v.53, pp.157 - 170, 2016-03

6

One-Cycle Correction of Timing Errors in Pipelines With Standard Clocked Elements

Shin, Insup; Kim, Jae Joon; Lin, Yu Shiang; Shin, YoungsooresearcherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INCIEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.24, no.2, pp.600 - 612, 2016-02

7

Light Interference Map: A Prescriptive Optimization of Lithography-Friendly Layout

Shim, Seongbo; Choi, Suhyeong; Shin, YoungsooresearcherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INCIEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, v.29, no.1, pp.44 - 49, 2016-02

8

An Analytical Approach to Thermal Design and Optimization With a Temperature-Dependent Power Model

Shim, Seongbo; Lee, Jae Wook; Shin, YoungsooresearcherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INCIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.62, no.3, pp.816 - 824, 2015-03

9

Aggressive Voltage Scaling Through Fast Correction of Multiple Errors With Seamless Pipeline Operation

Shin, In-Sup; Kim, Jae-Joon; Shin, YoungsooresearcherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INCIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.62, no.2, pp.468 - 477, 2015-02

10

Topology-oriented pattern extraction and classification for synthesizing lithography test patterns

Shim, Seongbo; Shin, YoungsooresearcherSPIE-SOC PHOTO-OPTICAL INSTRUMENTATION ENGINEERSJOURNAL OF MICRO-NANOLITHOGRAPHY MEMS AND MOEMS, v.14, no.1, 2015-01

11

Simplifying Clock Gating Logic by Matching Factored Forms

Han, Inhak; Shin, YoungsooresearcherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INCIEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.22, no.6, pp.1338 - 1349, 2014-06

12

HAPL: Heterogeneous Array of Programmable Logic Using Selective Mask Patterning

Shin, Youngsooresearcher; Shin, In-Sup; Baek, Donkyu; Kim, Duckhwan; Paik, SeungwhunIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INCIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.61, no.1, pp.146 - 159, 2014-01

13

ACCURATE GATE DELAY EXTRACTION FOR TIMING ANALYSIS OF BODY-BIASED CIRCUITS

Baek, Donkyu; Shin, Insup; Shin, YoungsooresearcherWORLD SCIENTIFIC PUBL CO PTE LTDJOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, v.22, no.8, 2013-09

14

Maximizing Frequency and Yield of Power-Constrained Designs Using Programmable Power-Gating

Kim, Nam-Sung; Sinkar, Abhishek; Seomun, Jun; Shin, Young-SooresearcherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INCIEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.20, no.10, pp.1885 - 1890, 2012-10

15

Clock Gating Synthesis of Pulsed-Latch Circuits

Paik, Seung-Whun; Han, In-Hak; Kim, Sang-Min; Shin, Young-SooresearcherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INCIEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.31, no.7, pp.1019 - 1030, 2012-07

16

HLS-dv: A High-Level Synthesis Framework for Dual-Vdd Architectures

Shin, In-Sup; Paik, Seung-Whun; Shin, Dong-Wan; Shin, Young-SooresearcherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INCIEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.20, no.4, pp.593 - 604, 2012-04

17

SAMPLING CORRELATION SOURCES FOR TIMING YIELD ANALYSIS OF SEQUENTIAL CIRCUITS WITH CLOCK NETWORKS

Yu, Lee-Eun; Shin, Chang-Sik; Paik, Seung-Whun; Liou, Jing-Jia; Shin, Young-SooresearcherWORLD SCIENTIFIC PUBL CO PTE LTDJOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, v.20, no.8, pp.1547 - 1569, 2011-12

18

Pulsed-Latch Aware Placement for Timing-Integrity Optimization

Chuang, Yi-Lin; Kim, Sangmin; Shin, Youngsooresearcher; Chang, Yao-WenIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INCIEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.30, no.12, pp.1856 - 1869, 2011-12

19

Retiming Pulsed-Latch Circuits with Regulating Pulse Width

Paik, Seung-Whun; Lee, Seong-Gwan; Shin, Young-SooresearcherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INCIEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.30, no.8, pp.1114 - 1127, 2011-08

20

Design and Optimization of Power-Gated Circuits With Autonomous Data Retention

Seomun, Jun; Shin, Young-SooresearcherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INCIEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.19, no.2, pp.227 - 236, 2011-02

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