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Park, In-Cheol (박인철) C-1549-2011

Department
School of Electrical Engineering(전기및전자공학부)
Co-author
Collaboration Network Collaboration Network
Website
http://ics.kaist.ac.krHomePage
Research Area

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1

Mismatch-tolerant Capacitor Array Structure for Junction-splitting SAR Analog-to-digital Conversion

Lee, Youngjoo; Oh, Taehyoun; Park, In-CheolresearcherIEEK PUBLICATION CENTERJOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v.17, no.3, pp.387 - 400, 2017-06

2

Multi-Bit Flipping Decoding of LDPC Codes for NAND Storage Systems

Jung, Jaehwan; Park, In-CheolresearcherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INCIEEE COMMUNICATIONS LETTERS, v.21, no.5, pp.979 - 982, 2017-05

3

High-Performance Low-Area Video Up-Scaling Architecture for 4-K UHD Video

Lee, Jooseung; Park, In-CheolresearcherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INCIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.64, no.4, pp.437 - 441, 2017-04

4

Improved Hard-Reliability Based Majority-Logic Decoding for Non-Binary LDPC Codes

Yeo, Saedong; Park, In-CheolresearcherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INCIEEE COMMUNICATIONS LETTERS, v.21, no.2, pp.230 - 233, 2017-02

5

Efficient Pruning for Successive-Cancellation Decoding of Polar Codes

Yoo , Hoyoung; Park, In-CheolresearcherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INCIEEE COMMUNICATIONS LETTERS, v.20, no.12, pp.2362 - 2365, 2016-12

6

Area-Efficient Approach for Generating Quantized Gaussian Noise

Choi, Jaejoon; Jung, Jaehwan; Park, In-CheolresearcherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INCIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.63, no.7, pp.1005 - 1013, 2016-07

7

Efficient Sorting Architecture for Successive-Cancellation-List Decoding of Polar Codes

Kong, Byeong Yong; Yoo, Hoyoung; Park, In-CheolresearcherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INCIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.63, no.7, pp.673 - 677, 2016-07

8

Fast detection for spatial modulation MIMO based on cost estimation

Kong, Byeong Yong; Park, In-CheolresearcherINST ENGINEERING TECHNOLOGY-IETELECTRONICS LETTERS, v.52, no.8, pp.671 - 672, 2016-04

9

Low-Power Parallel Chien Search Architecture Using a Two-Step Approach

Yoo, Hoyoung; Lee, Youngjoo; Park, In-CheolresearcherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INCIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.63, no.3, pp.269 - 273, 2016-03

10

Energy-Scalable 4KB LDPC Decoding Architecture for NAND-Flash-Based Storage Systems

Lee, Youngjoo; Jung, Jaehwan; Park, In-CheolresearcherIEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENGIEICE TRANSACTIONS ON ELECTRONICS, v.E99C, no.2, pp.293 - 301, 2016-02

11

Energy-Efficient Floating-Point MFCC Extraction Architecture for Speech Recognition Systems

Jo, Jihyuck; Yoo, Hoyoung; Park, In-CheolresearcherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INCIEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.24, no.2, pp.754 - 758, 2016-02

12

Reverse Rate Matching for Low-Power LTE-Advanced Turbo Decoders

Yoo, Injae; Kim, Bongjin; Park, In-CheolresearcherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INCIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.62, no.12, pp.2920 - 2928, 2015-12

13

Efficient Parallel Architecture for Linear Feedback Shift Registers

Jung, Jaehwan; Yoo, Hoyoung; Lee, Youngjoo; Park, In-CheolresearcherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INCIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.62, no.11, pp.1068 - 1072, 2015-11

14

Partially Parallel Encoder Architecture for Long Polar Codes

Yoo, Hoyoung; Park, In-CheolresearcherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INCIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.62, no.3, pp.306 - 310, 2015-03

15

Low-Complexity Tree Architecture for Finding the First Two Minima

Lee, Youngjoo; Kim, Bongjin; Jung, Jaehwan; Park, In-CheolresearcherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INCIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.62, no.1, pp.61 - 64, 2015-01

16

Area-efficient method to approximate two minima for LDPC decoders

Jung, Jaehwan; Lee, Youngjoo; Park, In-CheolresearcherINST ENGINEERING TECHNOLOGY-IETELECTRONICS LETTERS, v.50, no.23, pp.1701 - 121, 2014-11

17

Tail-Overlapped SISO Decoding for High-Throughput LTE-Advanced Turbo Decoders

Yoo, Injae; Kim, Bongjin; Park, In-CheolresearcherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INCIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.61, no.9, pp.2711 - 2720, 2014-09

18

Low-Complexity Low-Latency Architecture for Matching of Data Encoded With Hard Systematic Error-Correcting Codes

Kong, Byeong Yong; Jo, Jihyuck; Jeong, Hyewon; Hwang, Mina; Cha, Soyoung; Kim, Bongjin; Park, In-CheolresearcherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INCIEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.22, no.7, pp.1648 - 1652, 2014-07

19

Single-step glitch-free NAND-based digitally controlled delay lines using dual loops

Lee, Youngjoo; Park, In-CheolresearcherINST ENGINEERING TECHNOLOGY-IETELECTRONICS LETTERS, v.50, no.13, pp.930 - 931, 2014-06

20

High-Throughput and Low-Complexity BCH Decoding Architecture for Solid-State Drives

Lee, Youngjoo; Yoo, Hoyoung; Yoo, Injae; Park, In-CheolresearcherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INCIEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.22, no.5, pp.1183 - 1187, 2014-05

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