DC Field | Value | Language |
---|---|---|
dc.contributor.author | Yu, Chang-Hyo | ko |
dc.contributor.author | Chung, Kyusik | ko |
dc.contributor.author | Kim, Donghyun | ko |
dc.contributor.author | Kim, Seok-Hoon | ko |
dc.contributor.author | Kim, Lee-Sup | ko |
dc.date.accessioned | 2013-03-11T17:45:37Z | - |
dc.date.available | 2013-03-11T17:45:37Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2009-10 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.17, no.10, pp.1369 - 1382 | - |
dc.identifier.issn | 1063-8210 | - |
dc.identifier.uri | http://hdl.handle.net/10203/99770 | - |
dc.description.abstract | In this paper, a power efficient vertex processor for mobile graphics applications is presented. A four-threaded and four-issue expanded VLIW datapath with a quad-float vertex texture fetcher is proposed by exploiting graphics specific characteristics after evaluation of several candidate architectures. Instruction-level power control methods such as operand sharing and writeback re-allocation along with operand isolations and gated clocks result in 40.4% and 82% reduction in energy dissipation and energy delay product compared to the most widely used single threaded SIMD. The proposed processor with the optimized datapath and vertex caches implemented in a 0.18-mu m 1P4M CMOS process achieves 186-Mvertices/s geometry performance which is the best result among the processors that are IEEE-754 compliant. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | MOBILE APPLICATIONS | - |
dc.subject | SHADER | - |
dc.title | A 186-Mvertices/s 161-mW Floating-Point Vertex Processor With Optimized Datapath and Vertex Caches | - |
dc.type | Article | - |
dc.identifier.wosid | 000270037400001 | - |
dc.identifier.scopusid | 2-s2.0-70349756964 | - |
dc.type.rims | ART | - |
dc.citation.volume | 17 | - |
dc.citation.issue | 10 | - |
dc.citation.beginningpage | 1369 | - |
dc.citation.endingpage | 1382 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.identifier.doi | 10.1109/TVLSI.2008.2003515 | - |
dc.contributor.localauthor | Kim, Lee-Sup | - |
dc.contributor.nonIdAuthor | Yu, Chang-Hyo | - |
dc.contributor.nonIdAuthor | Kim, Donghyun | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Geometry processors | - |
dc.subject.keywordAuthor | 3-D graphics | - |
dc.subject.keywordAuthor | vertex caches | - |
dc.subject.keywordAuthor | vertex processors | - |
dc.subject.keywordAuthor | vertex shader | - |
dc.subject.keywordAuthor | VLIW | - |
dc.subject.keywordPlus | MOBILE APPLICATIONS | - |
dc.subject.keywordPlus | SHADER | - |
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