In this paper, a high-efficiency envelope-tracking (ET) transmitter incorporating a novel efficiency-boosting function is proposed and implemented. An inverse Class-F power amplifier is utilized and optimized using the proposed output loading condition, which enhances its efficiency at the high probability region. This matching network can be conveniently implemented by controlling the nonlinear capacitance of the power transistor. For an accurate analysis, the output waveforms are modeled in terms of the nonlinear capacitance, and the efficiency and output power are subsequently analyzed and successfully optimized. For a high-efficiency envelope amplifier (EA), we propose a new EA utilizing a 2-bit switching stage in place of a 1-bit switching stage. This proposed architecture effectively reduces the ripple current, improving the efficiency of the EA. To verify our analysis, we have fully implemented a 3.54-GHz high-efficiency ET transmitter including a digital processing block. The experimental results show that the ET transmitter using a commercial 60-W peak-envelope-power GaN device operates at a drain efficiency of 44% and power-added efficiency of 39.6% with a gain of 10.1 dB at an average output power of 40 dBm for a 10-MHz third-generation long-term evolution signal with 8.5-dB peak-to-average power ratio. Using a digital pre-distortion function, the adjacent channel leakage ratio is less than -47.5 dBc.