DC Field | Value | Language |
---|---|---|
dc.contributor.author | Chuang, Yi-Lin | ko |
dc.contributor.author | Kim, Sangmin | ko |
dc.contributor.author | Shin, Youngsoo | ko |
dc.contributor.author | Chang, Yao-Wen | ko |
dc.date.accessioned | 2013-03-11T12:14:04Z | - |
dc.date.available | 2013-03-11T12:14:04Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2011-12 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.30, no.12, pp.1856 - 1869 | - |
dc.identifier.issn | 0278-0070 | - |
dc.identifier.uri | http://hdl.handle.net/10203/99288 | - |
dc.description.abstract | Utilizing pulsed-latches in circuit designs is one emerging solution to timing improvements. Pulsed-latches, driven by a brief clock signal generated from pulse generators, possess superior design parameters over flip-flops. If the pulse generator and pulsed-latches are not placed properly, however, pulse-width degradations at pulsed-latches and thus timing violations might occur. In this paper, we present a unified placement framework for pulsed-latches to maintain the timing integrity. Our new placer has the following distinguished features: 1) a multilevel analytical placement framework to effectively prevent the potential pulse-width distortion problem; 2) a physical-location aware pulse-generator insertion algorithm to identify each desired group of a pulse generator and latches; and 3) a new optimization gradient for global placement to consider the impact of load capacitance of generators. Experimental results show that our placement flow can effectively consider pulse-width integrity and thus achieve much smaller total/worst negative slacks with marginal wirelength overheads, compared to a leading commercial and an academic placement flows. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | Pulsed-Latch Aware Placement for Timing-Integrity Optimization | - |
dc.type | Article | - |
dc.identifier.wosid | 000297336500007 | - |
dc.identifier.scopusid | 2-s2.0-82155192308 | - |
dc.type.rims | ART | - |
dc.citation.volume | 30 | - |
dc.citation.issue | 12 | - |
dc.citation.beginningpage | 1856 | - |
dc.citation.endingpage | 1869 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | - |
dc.contributor.localauthor | Shin, Youngsoo | - |
dc.contributor.nonIdAuthor | Chuang, Yi-Lin | - |
dc.contributor.nonIdAuthor | Chang, Yao-Wen | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Physical design | - |
dc.subject.keywordAuthor | placement | - |
dc.subject.keywordAuthor | pulsed-latch | - |
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