Runtime Power Management of 3-D Multi-Core Architectures Under Peak Power and Temperature Constraints

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3-D integration is a new technology that overcomes the limitations of 2-D integrated circuits, e.g., power and delay induced from long interconnect wires, by stacking multiple dies to increase logic integration density. However, chip-level power and peak temperature are the major performance limiters in 3-D multi-core architectures. In this paper, we propose a runtime power management method for both peak power and temperature-constrained 3-D multi-core systems in order to maximize the instruction throughput. The proposed method exploits dynamic temperature slack (defined as peak temperature constraint minus current temperature) and workload characteristics (e.g., instructions per cycle and memory-boundness) as well as thermal characteristics of 3-D stacking architectures. Compared with existing thermal-aware power management solutions for 3-D multi-core systems, our method yields up to 34.2% (average 18.5%) performance improvement in terms of instructions per second without significant additional energy consumption.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2011-06
Language
English
Article Type
Article
Keywords

THERMAL MANAGEMENT; PERFORMANCE; MICROARCHITECTURE; VOLTAGE; LEVEL

Citation

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.30, no.6, pp.905 - 918

ISSN
0278-0070
URI
http://hdl.handle.net/10203/99273
Appears in Collection
EE-Journal Papers(저널논문)
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