DC Field | Value | Language |
---|---|---|
dc.contributor.author | Pak, Jun-So | ko |
dc.contributor.author | Kim, Joo-Hee | ko |
dc.contributor.author | Cho, Jong-Hyun | ko |
dc.contributor.author | Kim, Ki-Yeong | ko |
dc.contributor.author | Song, Tai-Gon | ko |
dc.contributor.author | Ahn, Seung-Young | ko |
dc.contributor.author | Lee, Jun-Ho | ko |
dc.contributor.author | Lee, Hyung-Dong | ko |
dc.contributor.author | Park, Kun-Woo | ko |
dc.contributor.author | Kim, Joung-Ho | ko |
dc.date.accessioned | 2013-03-11T07:59:53Z | - |
dc.date.available | 2013-03-11T07:59:53Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2011-02 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, v.1, no.2, pp.208 - 219 | - |
dc.identifier.issn | 2156-3950 | - |
dc.identifier.uri | http://hdl.handle.net/10203/98713 | - |
dc.description.abstract | The impedance of a power-distribution network (PDN) in three-dimensionally stacked chips with multiple through-silicon-via (TSV) connections (a 3D TSV IC) was modeled and analyzed using a power/ground (P/G) TSV array model based on separated P/G TSV and chip-PDN models at frequencies up to 20 GHz. The proposed modeling and analysis methods for the P/G TSV and chip-PDN are fundamental for estimating the PDN impedances of 3D TSV ICs because they are composed of several chip-PDNs and several thousands of P/G TSV connections. Using the proposed P/G TSV array model, we obtained very efficient analyses and estimations of 3D TSV IC PDNs, including the effects of TSV inductance and multiple-TSV inductance, depending on P/G TSV arrangement and the number of stacked chip-PDNs of a 3D TSV IC PDN. Inductances related to TSVs, combined with chip-PDN inductance and capacitance, created high upper peaks of PDN impedance, near 1 GHz. Additionally, the P/G TSV array produced various TSV array inductance effects on stacked chip-PDN impedance, according to their arrangement, and induced high PDN impedance, over 10 GHz. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | POWER-DISTRIBUTION-NETWORK | - |
dc.subject | CIRCUIT MODELS | - |
dc.subject | SIGNAL | - |
dc.subject | TECHNOLOGY | - |
dc.subject | PACKAGE | - |
dc.title | PDN Impedance Modeling and Analysis of 3D TSV IC by Using Proposed P/G TSV Array Model Based on Separated P/G TSV and Chip-PDN Models | - |
dc.type | Article | - |
dc.identifier.wosid | 000292779200007 | - |
dc.identifier.scopusid | 2-s2.0-80155196172 | - |
dc.type.rims | ART | - |
dc.citation.volume | 1 | - |
dc.citation.issue | 2 | - |
dc.citation.beginningpage | 208 | - |
dc.citation.endingpage | 219 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY | - |
dc.identifier.doi | 10.1109/TCPMT.2010.2101771 | - |
dc.contributor.localauthor | Ahn, Seung-Young | - |
dc.contributor.localauthor | Kim, Joung-Ho | - |
dc.contributor.nonIdAuthor | Pak, Jun-So | - |
dc.contributor.nonIdAuthor | Lee, Jun-Ho | - |
dc.contributor.nonIdAuthor | Lee, Hyung-Dong | - |
dc.contributor.nonIdAuthor | Park, Kun-Woo | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Power distribution network (PDN) | - |
dc.subject.keywordAuthor | PDN impedance | - |
dc.subject.keywordAuthor | stacked chip-PDN | - |
dc.subject.keywordAuthor | through-silicon-via (TSV) | - |
dc.subject.keywordAuthor | TSV array inductance | - |
dc.subject.keywordAuthor | TSV inductance | - |
dc.subject.keywordAuthor | three-dimensional (3D) | - |
dc.subject.keywordAuthor | 3D TSV integrated circuit (IC) | - |
dc.subject.keywordPlus | POWER-DISTRIBUTION-NETWORK | - |
dc.subject.keywordPlus | CIRCUIT MODELS | - |
dc.subject.keywordPlus | SIGNAL | - |
dc.subject.keywordPlus | TECHNOLOGY | - |
dc.subject.keywordPlus | PACKAGE | - |
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