DC Field | Value | Language |
---|---|---|
dc.contributor.author | Choi, Sung-Jin | ko |
dc.contributor.author | Han, Jin-Woo | ko |
dc.contributor.author | Moon, Dong-Il | ko |
dc.contributor.author | Kim, Sung-Ho | ko |
dc.contributor.author | Jang, Moon-Gyu | ko |
dc.contributor.author | Choi, Yang-Kyu | ko |
dc.date.accessioned | 2013-03-09T14:54:11Z | - |
dc.date.available | 2013-03-09T14:54:11Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2010-08 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON ELECTRON DEVICES, v.57, no.8, pp.1737 - 1742 | - |
dc.identifier.issn | 0018-9383 | - |
dc.identifier.uri | http://hdl.handle.net/10203/96652 | - |
dc.description.abstract | A p-channel dopant-segregated-Schottky-barrier (DSSB) device based on a SOI FinFET structure is proposed for silicon-oxide-nitride-oxide-silicon type Flash memory, providing the feasibility of bit-by-bit operation through the aid of a symmetric program/erase operation. This concept is based on utilizing injected holes due to enhanced Fowler-Nordheim tunneling probability triggered by the sharpened energy band bending at the DSSB source/drain junctions as a programming method and the tunneled electrons from a silicon channel as an erasing method. As a result, a threshold voltage window of nearly 4 V and good data retention are achieved within a P/E time of 3.2 mu s. | - |
dc.language | English | - |
dc.publisher | IEEE-Inst Electrical Electronics Engineers Inc | - |
dc.subject | HIGH-PERFORMANCE | - |
dc.subject | FINFET | - |
dc.subject | SONOS | - |
dc.subject | TECHNOLOGY | - |
dc.title | P-Channel Nonvolatile Flash Memory With a Dopant-Segregated Schottky-Barrier Source/Drain | - |
dc.type | Article | - |
dc.identifier.wosid | 000283382800002 | - |
dc.identifier.scopusid | 2-s2.0-77955166011 | - |
dc.type.rims | ART | - |
dc.citation.volume | 57 | - |
dc.citation.issue | 8 | - |
dc.citation.beginningpage | 1737 | - |
dc.citation.endingpage | 1742 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON ELECTRON DEVICES | - |
dc.identifier.doi | 10.1109/TED.2010.2051331 | - |
dc.embargo.liftdate | 9999-12-31 | - |
dc.embargo.terms | 9999-12-31 | - |
dc.contributor.localauthor | Choi, Yang-Kyu | - |
dc.contributor.nonIdAuthor | Jang, Moon-Gyu | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Bit-by-bit | - |
dc.subject.keywordAuthor | dopant-segregation (DS) | - |
dc.subject.keywordAuthor | FinFET | - |
dc.subject.keywordAuthor | flash memory | - |
dc.subject.keywordAuthor | multilevel cell (MLC) | - |
dc.subject.keywordAuthor | NAND flash | - |
dc.subject.keywordAuthor | nickel silicidation | - |
dc.subject.keywordAuthor | nickel | - |
dc.subject.keywordAuthor | NiSi | - |
dc.subject.keywordAuthor | nonvolatile memory | - |
dc.subject.keywordAuthor | p-channel | - |
dc.subject.keywordAuthor | Schottky-barrier MOSFET | - |
dc.subject.keywordAuthor | Schottky-barrier | - |
dc.subject.keywordAuthor | silicon-oxide-nitride-oxide-silicon (SONOS) | - |
dc.subject.keywordAuthor | V(T) control | - |
dc.subject.keywordPlus | HIGH-PERFORMANCE | - |
dc.subject.keywordPlus | FINFET | - |
dc.subject.keywordPlus | SONOS | - |
dc.subject.keywordPlus | TECHNOLOGY | - |
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